C8051F988-GM Silicon Laboratories Inc, C8051F988-GM Datasheet - Page 295
![IC MCU 8BIT 4KB FLASH 24QFN](/photos/12/15/121587/c8051f9xx_24-qfn_sml.jpg)
C8051F988-GM
Manufacturer Part Number
C8051F988-GM
Description
IC MCU 8BIT 4KB FLASH 24QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F9xxr
Specifications of C8051F988-GM
Program Memory Type
FLASH
Program Memory Size
4KB (4K x 8)
Package / Case
24-UQFN Exposed Pad, 24-HUQFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F9x
Core
8051
Data Ram Size
512 B
Interface Type
I2C, SMBus, Enhanced UART, Enhanced SPI
Maximum Clock Frequency
7 KHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.4 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F996DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
On-chip Dac
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1959-5
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SFR Definition 25.13. TMR3CN: Timer 3 Control
SFR Page = 0x0; SFR Address = 0x91
Name
Reset
Bit
1:0 T3XCLK[1:0] Timer 3 External Clock Select.
Type
7
6
5
4
3
2
Bit
T3SPLIT
TF3CEN
TF3LEN
Name
TF3H
TF3L
TR3
TF3H
R/W
7
0
Timer 3 High Byte Overflow Flag.
Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the
Timer 3 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 3
interrupt service routine. This bit is not automatically cleared by hardware.
Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. TF3L will
be set when the low byte overflows regardless of the Timer 3 mode. This bit is not
automatically cleared by hardware.
Timer 3 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 3 Low Byte interrupts. If Timer 3 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 3 overflows.
Timer 3 SmaRTClock/External Oscillator Capture Enable.
When set to 1, this bit enables Timer 3 Capture Mode.
Timer 3 Split Mode Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
0: Timer 3 operates in 16-bit auto-reload mode.
1: Timer 3 operates as two 8-bit auto-reload timers.
Timer 3 Run Control.
Timer 3 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR3H only; TMR3L is always enabled in split mode.
This bit selects the “external” and “capture trigger” clock sources for Timer 3. If
Timer 3 is in 8-bit mode, this bit selects the “external” clock source for both timer
bytes. Timer 3 Clock Select bits (T3MH and T3ML in register CKCON) may still be
used to select between the “external” clock and the system clock for either timer.
Note: External clock sources are synchronized with the system clock.
00: External Clock is SYSCLK /12. Capture trigger is SmaRTClock.
01: External Clock is External Oscillator/8. Capture trigger is SmaRTClock.
10: External Clock is SYSCLK/12. Capture trigger is External Oscillator/8.
11: External Clock is SmaRTClock. Capture trigger is External Oscillator/8.
TF3L
R/W
6
0
TF3LEN
R/W
5
0
TF3CEN
R/W
Rev. 1.0
4
0
C8051F99x-C8051F98x
Function
T3SPLIT
R/W
3
0
TR3
R/W
2
0
1
0
T3XCLK[1:0]
R/W
0
0
295
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