C8051F988-GM Silicon Laboratories Inc, C8051F988-GM Datasheet - Page 299
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C8051F988-GM
Manufacturer Part Number
C8051F988-GM
Description
IC MCU 8BIT 4KB FLASH 24QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F9xxr
Specifications of C8051F988-GM
Program Memory Type
FLASH
Program Memory Size
4KB (4K x 8)
Package / Case
24-UQFN Exposed Pad, 24-HUQFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F9x
Core
8051
Data Ram Size
512 B
Interface Type
I2C, SMBus, Enhanced UART, Enhanced SPI
Maximum Clock Frequency
7 KHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.4 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F996DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
On-chip Dac
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1959-5
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26.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2–CPS0 bits in the PCA0MD
register select the timebase for the counter/timer as shown in Table 26.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by
software. Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while
the CPU is in Idle mode.
Notes:
S YS C LK /12
S YS C LK /4
Tim er 0 O verflow
E C I
S YS C LK
E xternal C lock/8
S m aR TC lock/8
CPS2
1. External oscillator source divided by 8
2. SmaRTClock oscillator source divided by 8
0
0
0
0
1
1
1
1
C
D
L
I
W
D
T
E
CPS1
P C A 0M D
W
D
C
K
L
0
0
1
1
0
0
1
1
C
P
S
2
000
001
010
011
100
101
110
C
P
S
1
C
P
S
0
C
E
F
Figure 26.2. PCA Counter/Timer Block Diagram
CPS0
Table 26.1. PCA Timebase Input Options
0
1
0
1
0
1
0
1
ID LE
C
F
C
R
P C A 0C N
Timebase
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock divided
by 4)
System clock
C
C
F
2
C
C
F
1
C
C
F
0
SmaRTClock oscillator source divided by 8
is
External oscillator source divided by 8
synchronized with the system clock.
Rev. 1.0
0
1
P C A 0L
is
read
synchronized with the system clock.
C8051F99x-C8051F98x
S napshot
R egister
P C A 0H
Reserved
P C A 0L
To S FR Bus
T o P C A M odules
O verflow
C F
1
To P C A Interrupt S ystem
2
299
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