AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 1065

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

50.2.12
50.2.12.1
50.2.12.2
50.2.13
50.2.13.1
50.2.13.2
50.2.13.3
6249H–ATARM–27-Jul-09
ROM Code
SDRAM Controller
SDCard Boot is Not Functional
NAND Flash Boot is Not Functional
SDCLK Clock Active after Reset
Mobile SDRAM Device Initialization Constraint
JEDEC Standard Compatibility
leads to a bad reset of the Embedded Trace Macrocell (ETM9). The ARM processor then enters
debug state and the device does not boot correctly.
SDCard Boot is not functional in this revision.
None.
NAND Flash Boot is not functional in this revision.
None.
After a reset, the SDRAM clock is always active leading to overconsumption in the pad.
The following sequence stops the SDRAM clock:
Using Mobile SDRAM devices that need to have their DQMx level HIGH during Mobile SDRAM
device initialization may lead to data bus contention and thus external memories on the same
EBI must not be accessed.
This does not apply to Mobile SDRAM devices whose DQMx level is “Don’t care” during this
phase.
Mobile SDRAM initialization must be performed in internal SRAM.
In the current configuration, SDCKE rises at the same time as SDCK while exiting self-refresh
mode. To be fully compliant with the JEDEC standard, SDCK must be STABLE before the rising
edge of SDCKE.
It is not the case in this product.
Use a fully JEDEC compliant SDRAM module.
1. Connect NTRST pin to NRST pin to ensure that a correct powering sequence takes
2. Connect NTRST to GND if no debug capabilities are required.
1. Set the bit LPCB in the SDRAMC Low Power Register.
2. Write 0 in the SDRAMC Mode Register and perform a dummy write in SDRAM to
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
place in all cases.
complete.
AT91SAM9263
1065