AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 251

IC ARM9 MCU 200 MHZ 324-TFBGA

AT91SAM9263B-CU

Manufacturer Part Number
AT91SAM9263B-CU
Description
IC ARM9 MCU 200 MHZ 324-TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheets

Specifications of AT91SAM9263B-CU

Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
2-Wire, EBI, I2S, MCI, SPI, USART
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
Minimum Operating Temperature
- 40 C
Package
324TFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
200 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
Controller Family/series
AT91SAM9xxx
No. Of I/o's
160
Ram Memory Size
96KB
Cpu Speed
240MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q3735625

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23.6.4
Register Name:SDRAMC_LPR
Addresses: 0xFFFFE210 (0), 0xFFFFE810 (1)
Access Type:Read-write
Reset Value: 0x0
• LPCB: Low-power Configuration Bits
• PASR: Partial Array Self-refresh (only for low-power SDRAM)
PASR parameter is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks
of the SDRAM array are enabled. Disabled banks are not refreshed in self-refresh mode. This parameter must be set
according to the SDRAM device specification.
• TCSR: Temperature Compensated Self-Refresh (only for low-power SDRAM)
TCSR parameter is transmitted to the SDRAM during initialization to set the refresh interval during self-refresh mode
depending on the temperature of the low-power SDRAM. This parameter must be set according to the SDRAM device
specification.
• DS: Drive Strength (only for low-power SDRAM)
DS parameter is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parame-
ter must be set according to the SDRAM device specification.
6249H–ATARM–27-Jul-09
00
01
10
11
31
23
15
7
SDRAMC Low Power Register
Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to
the SDRAM device.
The SDRAM Controller issues a Self-refresh command to the SDRAM device, the SDCLK clock is
deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when
accessed and enters it after the access.
The SDRAM Controller issues a Power-down Command to the SDRAM device after each access, the
SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and
enters it after the access.
The SDRAM Controller issues a Deep Power-down command to the SDRAM device. This mode is
unique to low-power SDRAM.
30
22
14
6
PASR
29
21
13
5
TIMEOUT
28
20
12
4
27
19
11
3
DS
26
18
10
2
AT91SAM9263
25
17
9
1
TCSR
LPCB
24
16
8
0
251

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