AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 1076

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

50.3.8.2
50.3.8.3
50.3.9
50.3.9.1
1076
AT91SAM9263
MCI
LCD Periodic Bad Pixels
24-bit Packed Mode
Busy signal of R1b responses is not taken in account
LCD periodic bad pixels is due to mis-aligned DMA base address in frame buffer. LCD DMA per-
forms bursts to read memory. These bursts must not cross 1Kb AMBA boundary.
The burst size in 32-bit words is programmed by field BRSTLN in DMAFRMCFG register.
The LCD DMA Base Address is programmed in DMABADDR1 register.
DMA Base Address must be programmed with a value aligned onto LCD DMA burst size.
e.g.:
BRSTLN = 15
For a 16-word burst, the LCD DMA Base Address must start on 16-word offset: 0x0, 0x40, 0x80
or 0xc0.
BRSTLN = 3
For a 4-word burst, the LCD DMA Base Address must start on 0x0, 0x10, ..., 0xf0.
LCD DMA Base Address and LCD DMA burst size must be selected with care in 24-bit packed
mode. A 32-bit word contains some bits of a pixel and some bits of the following. If LCD DMA
Base Address is not aligned with a pixel start, the colors will be modified.
Respect "LCD periodic bad pixels" erratum constraints lead to select the LCD DMA Base
Address regarding the LCD DMA burst size.
LCD DMA Base Address is to be set on a pixel start, every three 32-bit word.
The offset of the LCD DMA Base Address must be a multiple of 0x30 plus 0x0, 0xc, 0x18 or
0x24. (0x0, 0xc, 0x18, 0x24, 0x30, 0x3c, 0x48, 0x54, 0x60,0x6c, 0x78, 0x84, 0x90, 0x9c, 0xa8,
0xb4, 0xc0 ...)
e.g. regarding the bursts size:
1) BRSTLN = 3 implies the following LCD DMA Base Address offsets: 0x0, 0x30, 0x60, ...
2) BRSTLN = 15 implies the following LCD DMA Base Address offsets: 0x0 and 0xc0 only
The busy status of the card during the response (R1b) is ignored for the commands CMD7,
CMD28, CMD29, CMD38, CMD42, CMD56.
Additionally, for commands CMD42 and CMD56, a conflict can occur on data line 0 if the MCI
sends data to the card while the card is still busy.
The behavior is correct for CMD12 command (STOP_TRANSFER).
None
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6249H–ATARM–27-Jul-09