AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 867
AT91SAM9263B-CU
Manufacturer Part Number
AT91SAM9263B-CU
Description
IC ARM9 MCU 200 MHZ 324-TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9263B-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
2-Wire, EBI, I2S, MCI, SPI, USART
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
Minimum Operating Temperature
- 40 C
Package
324TFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
200 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
Controller Family/series
AT91SAM9xxx
No. Of I/o's
160
Ram Memory Size
96KB
Cpu Speed
240MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q3735625
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9263B-CU
Manufacturer:
IDT
Quantity:
1 043
Part Number:
AT91SAM9263B-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
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Company:
Part Number:
AT91SAM9263B-CU-100
Manufacturer:
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Quantity:
1 000
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Figure 43-6. Data IN Transfer for Non Ping-pong Endpoint
43.5.2.4
867
USB Bus Packets
TXPKTRDY Flag
(UDP_CSRx)
TXCOMP Flag
(UDP_CSRx)
FIFO (DPR)
Content
AT91SAM9263
Using Endpoints With Ping-pong Attribute
Set by the firmware
Data IN
PID
Prevous Data IN TX
Data IN 1
Interrupt Pending
The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. This
also allows handling the maximum bandwidth defined in the USB specification during bulk trans-
fer. To be able to guarantee a constant or the maximum bandwidth, the microcontroller must
prepare the next data payload to be sent while the current one is being sent by the USB device.
Thus two banks of memory are used. While one is available for the microcontroller, the other
one is locked by the USB device.
Figure 43-7. Bank Swapping Data IN Transfer for Ping-pong Endpoints
When using a ping-pong endpoint, the following procedures are required to perform Data IN
transactions:
Cleared by Hw
Data IN 1
Microcontroller
1 st Data Payload
2 nd Data Payload
3 rd Data Payload
DPR access by the firmware
ACK
PID
Load In Progress
Set by the firmware
Microcontroller Load Data in FIFO
Data IN
PID
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Write
NAK
PID
Cleared by Firmware
USB Device
Data IN
PID
DPR access by the hardware
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Read
Read and Write at the Same Time
Data is Sent on USB Bus
Data IN 2
Payload in FIFO
Data IN 2
USB Bus
Cleared by Hw
2 nd Data Payload
3 rd Data Payload
1 st Data Payload
Data IN Packet
Data IN Packet
Data IN Packet
6249H–ATARM–27-Jul-09
ACK
PID
Cleared by
Firmware
Interrupt
Pending
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