AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 231

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

22.14.4
Register Name:SMC_MODE[0..7]
Addresses: 0xFFFFE40C (0)[0], 0xFFFFE41C (0)[1], 0xFFFFE42C (0)[2], 0xFFFFE43C (0)[3], 0xFFFFE44C (0)[4],
0xFFFFE45C (0)[5], 0xFFFFE46C (0)[6], 0xFFFFE47C (0)[7], 0xFFFFEA0C (1)[0], 0xFFFFEA1C (1)[1], 0xFFFFEA2C
(1)[2], 0xFFFFEA3C (1)[3], 0xFFFFEA4C (1)[4], 0xFFFFEA5C (1)[5], 0xFFFFEA6C (1)[6], 0xFFFFEA7C (1)[7]
Access Type:Read-write
• READ_MODE:
1: The read operation is controlled by the NRD signal.
0: The read operation is controlled by the NCS signal.
• WRITE_MODE
1: The write operation is controlled by the NWE signal.
0: The write operation is controlled by the NCS signal.
• EXNW_MODE: NWAIT Mode
The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of
the read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be pro-
grammed for the read and write controlling signal.
6249H–ATARM–27-Jul-09
• Disabled Mode: The NWAIT input signal is ignored on the corresponding Chip Select.
• Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write
cycle is resumed from the point where it was stopped.
– If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NRD.
– If TDF cycles are programmed, the external bus is marked busy after the rising edge of NCS.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NCS.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NWE.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NCS.
31
23
15
–
–
–
7
–
SMC MODE Register
0
0
1
1
EXNW_MODE
30
22
14
–
–
–
6
–
0
1
0
1
29
21
13
–
5
EXNW_MODE
DBW
PS
TDF_MODE
NWAIT Mode
Disabled
Reserved
Frozen Mode
Ready Mode
28
20
12
4
27
19
11
–
–
3
–
26
18
10
–
–
2
–
TDF_CYCLES
WRITE_MODE
AT91SAM9263
25
17
–
9
–
1
READ_MODE
PMEN
BAT
24
16
8
0
231