AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 234

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

23.3
23.3.1
23.3.1.1
Table 23-2.
Table 23-3.
Table 23-4.
Notes:
234
27
27
27
Bk[1:0]
26
26
26
Bk[1:0]
Bk[1:0]
Application Example
1. M[1:0] is the byte address inside a 32-bit word.
3. Bk[1] = BA1, Bk[0] = BA0.
AT91SAM9263
25
25
25
Software Interface
Bk[1:0]
Bk[1:0]
Bk[1:0]
32-bit Memory Data Bus Width
24
24
24
SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
Bk[1:0]
Bk[1:0]
Bk[1:0]
23
23
23
Bk[1:0]
Bk[1:0]
22
22
22
Bk[1:0]
The SDRAM address space is organized into banks, rows, and columns. The SDRAM controller
allows mapping different memory types according to the values set in the SDRAMC configura-
tion register.
The SDRAM Controller’s function is to make the SDRAM device access protocol transparent to
the user.
user in correlation with the device structure. Various configurations are illustrated.
21
21
21
20
20
20
Row[12:0]
Row[11:0]
Table 23-2
19
19
19
Row[10:0]
Row[12:0]
Row[11:0]
18
18
18
Row[10:0]
Row[12:0]
Row[11:0]
17
17
17
Row[10:0]
Row[12:0]
to
Row[11:0]
16
16
16
Table 23-7
Row[10:0]
15
15
15
CPU Address Line
CPU Address Line
CPU Address Line
14
14
14
illustrate the SDRAM device memory mapping seen by the
13
13
13
12
12
12
11
11
11
10
10
10
9
9
9
8
8
8
Column[10:0]
Column[10:0]
Column[10:0]
Column[9:0]
Column[9:0]
Column[9:0]
7
7
7
Column[8:0]
Column[8:0]
Column[8:0]
Column[7:0]
Column[7:0]
Column[7:0]
6
6
6
5
5
5
4
4
4
6249H–ATARM–27-Jul-09
3
3
3
2
2
2
1
1
1
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
0
0
0