AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 274

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

25.3.3.3
25.3.3.4
25.3.3.5
274
AT91SAM9263
Single Transactions
External DMA Request Definition
Hardware Handshaking
Y o u c a n w r i te a 1 t o th e D M A C _ S gl R e q S rc R eg [ x ]/ D M A C _ S g l R e qD s tR e g [x ] a n d
DMAC_ReqSrcReg[x]/DMAC_ReqDstReg[x] registers in any order, but both registers must be
asserted in order to initiate a burst transaction. Upon completion of the burst transaction, the
h a r d w a r e c l e a r s t h e D M A C _ S g l R e q S r c R e g [ x ] / D M A C _ S g l R e q D s t R e g [ x ] a n d
DMAC_ReqSrcReg[x]/DMAC_ReqDstReg[x] registers.
Writing a 1 to the DMAC_SglReqSrcReg/DMAC_SglReqDstReg initiates a single transaction.
U p o n
DMAC_SglReqSrcReg/DMAC_SglReqDstReg and DMAC_ReqSrcReg/DMAC_ReqDstReg bits
are cleared by hardware. Therefore, writing a 1 to the DMAC_ReqSrcReg/DMAC_ReqDstReg is
ignored while a single transaction has been initiated, and the requested burst transaction is not
serviced.
Again, writing a 1 to the DMAC_ReqSrcReg/DMAC_ReqDstReg register is always a burst trans-
action request. However, in order for a burst transaction request to start, the corresponding
channel bit in the DMAC_SglReqSrcReg/DMAC_SglReqDstReg must be asserted. Therefore, to
e n s u r e t h a t a b u r s t t r a n s a c t i o n i s s e r v i c e d , y o u m u s t w r i t e a 1 t o t h e
D M A C _ R e q S r c R e g / D M A C _ R e q D s t R e g
DMAC_SglReqSrcReg/DMAC_SglReqDstReg register.
Software can poll the relevant channel bit in the DMAC_SglReqSrcReg/ DMAC_SglReqDstReg
and DMAC_ReqSrcReg/DMAC_ReqDstReg registers. When both are 0, then either the
requested burst or single transaction has completed. Alternatively, the IntSrcTran or IntDstTran
interrupts can be enabled and unmasked in order to generate an interrupt when the requested
source or destination transaction has completed.
Note:
There are 5 hardware handshaking interfaces connected to four external DMA requests (see
Table
Table 25-1.
When an external slave peripheral requires the DMAC to perform DMA transactions, it communi-
cates its request by asserting the external nDMAREQx signal. This signal is resynchronized to
ensure a proper functionality (see
The external nDMAREQx is asserted when the source threshold level is reached. After resyn-
chronization, the rising edge of dma_req starts the transfer. dma_req is de-asserted when
dma_ack is asserted.
Request
DMAREQ0
DMAREQ1
DMAREQ2
DMAREQ3
25-1).
The transaction-complete interrupts are triggered when both single and burst transactions are
complete. The same transaction-complete interrupt is used for both single and burst transactions.
c o m p l e t i o n
Hardware Handshaking Connection
Definition
External DMA Request 0
External DMA Request 1
External DMA Request 2
External DMA Request 3
o f
Figure 25-4 on page
t h e
s i n g l e
b e f o r e
275).
t r a n s a c t i o n ,
w r i t i n g
Hardware Handshaking
a
6249H–ATARM–27-Jul-09
Interface
1
b o t h
1
2
3
4
t o
t h e
t h e