AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 310

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

0 = Hardware handshaking interface. Software-initiated transaction requests are ignored.
1 = Software handshaking interface. Hardware-initiated transaction requests are ignored.
If the source peripheral is memory, then this bit is ignored.
• LOCK_CH_L: Channel Lock Level
Indicates the duration over which DMAC_CFGx.LOCK_CH bit applies.
00 = Over complete DMA transfer
01 = Over complete DMA block transfer
1x = Over complete DMA transaction
• LOCK_B_L: Bus Lock Level
Indicates the duration over which DMAC_CFGx.LOCK_B bit applies.
00 = Over complete DMA transfer
01 = Over complete DMA block transfer
1x = Over complete DMA transaction
• LOCK_CH: Channel Lock Bit
When the channel is granted control of the master bus interface and if the DMAC_CFGx.LOCK_CH bit is asserted, then no
other channels are granted control of the master bus interface for the duration specified in DMAC_CFGx.LOCK_CH_L.
Indicates to the master bus interface arbiter that this channel wants exclusive access to the master bus interface for the
duration specified in DMAC_CFGx.LOCK_CH_L.
• LOCK_B: Bus Lock Bit
When active, the AMBA bus master signal hlock is asserted for the duration specified in DMAC_CFGx.LOCK_B_L.
• DS_HS_POL: Destination Handshaking Interface Polarity
0 = Active high
1 = Active low
• SR_HS_POL: Source Handshaking Interface Polarity
0 = Active high
1 = Active low
• MAX_ABRST: Maximum AMBA Burst Length
Maximum AMBA burst length that is used for DMA transfers on this channel. A value of ‘0’ indicates that software is not lim-
iting the maximum AMBA burst length for DMA transfers on this channel.
• RELOAD_SR: Automatic Source Reload
The DMAC_SARx register can be automatically reloaded from its initial value at the end of every block for multi-block trans-
fers. A new block transfer is then initiated.
• RELOAD_DS: Automatic Destination Reload
The DMAC_DARx register can be automatically reloaded from its initial value at the end of every block for multi-block
transfers. A new block transfer is then initiated.
AT91SAM9263
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6249H–ATARM–27-Jul-09