S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 105

• Manufacturer Part Number: S9S12HY64J0MLH
• Description: MCU 64K FLASH AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLH

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: S12
• No. Of I/o's: 50
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
1
2.3.53
2.3.54
2.3.55
Freescale Semiconductor
Address 0x0275
RDR1AD
Address 0x0276
Address 0x0277
Read: Anytime
Write: Anytime
Read: Always reads 0x00
Write: Unimplemented
Field
Reset
Reset
Reset
7-0
W
W
W
R
R
R
RDR1AD7
PER1AD7
Port AD reduced drive—Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (1/6 of the full drive strength)
0 Full drive strength enabled
Port AD Reduced Drive Register (RDR1AD)
PIM Reserved Register
Port AD Pull Up Enable Register (PER1AD)
0
0
0
0
7
7
7
= Unimplemented or Reserved
RDR1AD6
PER1AD6
Figure 2-51. Port AD Reduced Drive Register (RDR1AD)
Figure 2-53. Port AD Pull Up Enable Register (PER1AD)
0
0
0
0
6
6
6
Table 2-45. RDR1AD Register Field Descriptions
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
RDR1AD5
PER1AD5
Figure 2-52. PIM Reserved Register
0
0
0
0
5
5
5
RDR1AD4
PER1AD4
0
0
0
0
4
4
4
Description
RDR1AD3
PER1AD3
3
0
3
0
0
3
0
RDR1AD2
PER1AD2
Port Integration Module (S12HYPIMV1)
0
0
0
0
2
2
2
RDR1AD1
PER1AD1
Access: User read/write
Access: User read/write
0
0
0
0
1
1
1
Access: User read
RDR1AD0
PER1AD0
0
0
0
0
0
0
0
105
1
1
1