HD64F36912GFH Renesas Electronics America, HD64F36912GFH Datasheet - Page 11

• Manufacturer Part Number: HD64F36912GFH
• Description: IC H8 MCU FLASH 8K 32-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F36912GFH

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 12MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 1 Overview................................................................................................1
1.1
1.2
1.3
1.4
Section 2 CPU......................................................................................................11
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Section 3 Exception Handling .............................................................................47
3.1
3.2
Features................................................................................................................................. 1
Internal Block Diagram......................................................................................................... 3
Pin Arrangement ................................................................................................................... 5
Pin Functions ........................................................................................................................ 9
Address Space and Memory Map ....................................................................................... 12
Register Configuration........................................................................................................ 14
2.2.1
2.2.2
2.2.3
Data Formats....................................................................................................................... 18
2.3.1
2.3.2
Instruction Set ..................................................................................................................... 21
2.4.1
2.4.2
Addressing Modes and Effective Address Calculation....................................................... 32
2.5.1
2.5.2
Basic Bus Cycle .................................................................................................................. 37
2.6.1
2.6.2
CPU States .......................................................................................................................... 39
Usage Notes ........................................................................................................................ 40
2.8.1
2.8.2
2.8.3
Exception Sources and Vector Address .............................................................................. 47
Register Descriptions.......................................................................................................... 49
3.2.1
3.2.2
3.2.3
General Registers................................................................................................ 15
Program Counter (PC) ........................................................................................ 16
Condition-Code Register (CCR)......................................................................... 16
General Register Data Formats ........................................................................... 18
Memory Data Formats ........................................................................................ 20
Table of Instructions Classified by Function ...................................................... 21
Basic Instruction Formats ................................................................................... 30
Addressing Modes .............................................................................................. 32
Effective Address Calculation ............................................................................ 35
Access to On-Chip Memory (RAM, ROM)........................................................ 37
On-Chip Peripheral Modules .............................................................................. 38
Notes on Data Access to Empty Areas ............................................................... 40
EEPMOV Instruction.......................................................................................... 40
Bit Manipulation Instruction............................................................................... 40
Interrupt Edge Select Register 1 (IEGR1) .......................................................... 49
Interrupt Edge Select Register 2 (IEGR2) .......................................................... 50
Interrupt Enable Register 1 (IENR1) .................................................................. 50
Contents
Rev. 3.00 Sep. 14, 2006 Page ix of xxviii