HD64F36912GFH Renesas Electronics America, HD64F36912GFH Datasheet - Page 27

• Manufacturer Part Number: HD64F36912GFH
• Description: IC H8 MCU FLASH 8K 32-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F36912GFH

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 12MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 1 Overview
Table 1.1
Section 2 CPU
Table 2.1
Table 2.2
Table 2.3
Table 2.3
Table 2.4
Table 2.5
Table 2.6
Table 2.6
Table 2.7
Table 2.8
Table 2.9
Table 2.10
Table 2.11
Table 2.12
Table 2.12
Section 3 Exception Handling
Table 3.1
Table 3.2
Section 4 Address Break
Table 4.1
Section 5 Clock Pulse Generators
Table 5.1
Section 6 Power-Down Modes
Table 6.1
Table 6.2
Table 6.3
Section 7 ROM
Table 7.1
Table 7.2
Table 7.3
Pin Functions ............................................................................................................ 9
Operation Notation ................................................................................................. 21
Data Transfer Instructions....................................................................................... 22
Arithmetic Operations Instructions (1) ................................................................... 23
Arithmetic Operations Instructions (2) ................................................................... 24
Logic Operations Instructions................................................................................. 25
Shift Instructions..................................................................................................... 25
Bit Manipulation Instructions (1)............................................................................ 26
Bit Manipulation Instructions (2)............................................................................ 27
Branch Instructions ................................................................................................. 28
System Control Instructions.................................................................................... 29
Block Data Transfer Instructions ............................................................................ 30
Addressing Modes .................................................................................................. 32
Absolute Address Access Ranges ........................................................................... 34
Effective Address Calculation (1)........................................................................... 35
Effective Address Calculation (2)........................................................................... 36
Exception Sources and Vector Address .................................................................. 47
Interrupt Wait States ............................................................................................... 59
Access and Data Bus Used ..................................................................................... 65
Crystal Resonator Parameters ................................................................................. 82
Operating Frequency and Wait Time...................................................................... 87
Transition Mode after SLEEP Instruction Execution and Interrupt Handling ........ 92
Internal State in Each Operating Mode................................................................... 92
Setting Programming Modes ................................................................................ 102
Boot Mode Operation ........................................................................................... 104
System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible ................................................................................................................. 105
Tables
Rev. 3.00 Sep. 14, 2006 Page xxv of xxviii