HD64F36912GFH Renesas Electronics America, HD64F36912GFH Datasheet - Page 95

• Manufacturer Part Number: HD64F36912GFH
• Description: IC H8 MCU FLASH 8K 32-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F36912GFH

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 12MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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X:
When an address break is set in the data read cycle or data write cycle, the data bus used will
depend on the combination of the byte/word access and address. Table 4.1 shows the access and
data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a
byte access is generated twice. For details on data widths of each register, see section 19.1,
Register Addresses (Address Order).
Table 4.1
Bit
1
0
ROM space
RAM space
I/O register with 8-bit data bus
width
I/O register with 16-bit data
bus width
Don't care
Bit Name
DCMP1
DCMP0
Access and Data Bus Used
Initial
Value
0
0
R/W
R/W
R/W
Even Address Odd Address
Upper 8 bits
Upper 8 bits
Upper 8 bits
Upper 8 bits
Word Access
Description
Data Compare Condition Select 1 and 0
These bits set the comparison condition between the data
set in BDR and the internal data bus.
00: No data comparison
01: Compares lower 8-bit data between BDRL and data
10: Compares upper 8-bit data between BDRH and data
11: Compares 16-bit data between BDR and data bus
bus
bus
Lower 8 bits
Lower 8 bits
Upper 8 bits
Lower 8 bits
Rev. 3.00 Sep. 14, 2006 Page 65 of 408
Even Address Odd Address
Upper 8 bits
Upper 8 bits
Upper 8 bits
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Section 4 Address Break
Byte Access
REJ09B0105-0300
Upper 8 bits
Upper 8 bits
Upper 8 bits
—