HD64F36912GFH Renesas Electronics America, HD64F36912GFH Datasheet - Page 297

• Manufacturer Part Number: HD64F36912GFH
• Description: IC H8 MCU FLASH 8K 32-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F36912GFH

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 12MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Clear ACKBT in ICIER to 0
Clear RCVD in ICCR1 to 0
Set ACKBT in ICIER to 1
Clear MST in ICCR1 to 0
Clear TRS in ICCR1 to 0
Set RCVD in ICCR1 to 1
No
No
No
Clear STOP in ICSR.
Clear TEND in ICSR
Clear TDRE in ICSR
Dummy-read ICDRR
Read RDRF in ICSR
Read RDRF in ICSR
Read STOP in ICSR
Mater receive mode
Write 0 to BBSY
Read ICDRR
Read ICDRR
Read ICDRR
RDRF=1 ?
Last receive
RDRF=1 ?
STOP=1 ?
and SCP
End
- 1?
Supplementary explanation:
Yes
Yes
Yes
No
Figure 15.18 Sample Flowchart for Master Receive Mode
Yes
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Note: Do not activate an interrupt during the execution of steps [1] to [3].
[1] Clear TEND, select master receive mode, and then clear TDRE.*
[2] Set acknowledge to the transmit device.*
[3] Dummy-read ICDDR.*
[4] Wait for 1 byte to be received
[5] Check whether it is the (last receive - 1).
[6] Read the receive data last.
[7] Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).
[8] Read the (final byte - 1) of receive data.
[9] Wait for the last byte to be receive.
[10] Clear the STOP flag.
[11] Issue the stop condition.
[12] Wait for the creation of stop condition.
[13] Read the last byte of receive data.
[14] Clear RCVD.
[15] Set slave receive mode.
When one byte is received, steps [2] to [6] are skipped after step [1],
before jumping to step [7]. The step [8] is dammy-read in ICDRR.
Rev. 3.00 Sep. 14, 2006 Page 267 of 408
Section 15 I
2
C Bus Interface 2 (IIC2)
REJ09B0105-0300