HD64F36912GFH Renesas Electronics America, HD64F36912GFH Datasheet - Page 322
HD64F36912GFH
Manufacturer Part Number
HD64F36912GFH
Description
IC H8 MCU FLASH 8K 32-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36912GFHV.pdf
(442 pages)
Specifications of HD64F36912GFH
Core Processor
H8/300H
Core Size
16-Bit
Speed
12MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F36912GFH
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits
17.3.2
(1)
Figure 17.4 shows the timing of the operation of the LVDR circuit. The LVDR circuit is enabled
after a power-on reset is released. To cancel the LVDR circuit, first the LVDRE bit in LVDCR
should be cleared to 0 and then the LVDE bit in LVDCR and, if necessary, the BGRE bit should
be cleared to 0. The LVDE and the BGRE bits must not be cleared to 0 simultaneously with the
LVDRE bit because incorrect operation may occur. To restart the LVDR circuit, set the LVDE bit
and the BGRE bit to 1, wait for 50 s (t
and the low-voltage-detection power supply have settled, then set the LVDRE bit to 1. After that,
the output settings of ports must be made.
When the power-supply voltage falls below the Vreset voltage (2.3 V or 3.6 V (Typ.)), the LVDR
circuit clears the LVDRES signal to 0, and resets prescaler S. The low-voltage detection reset state
remains in place until a power-on reset is generated. When the power-supply voltage rises above
the Vreset voltage again, prescaler S starts counting. It counts 131,072 clock ( ) cycles, and then
releases the internal reset signal. In this case, the LVDE, BGRE, VDDII, LVDSEL, and LVDRE
bits in LVDCR are not initialized.
Note that if the power supply voltage (Vcc) falls below V
point, the low-voltage detection reset may not occur.
If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.
Rev. 3.00 Sep. 14, 2006 Page 292 of 408
REJ09B0105-0300
RES
Vcc
PSS-reset
signal
OVF
Internal reset
signal
LVDR (Reset by Low Voltage Detection) Circuit
Low-Voltage Detection Circuit
Vpor
t
PWON
Figure 17.3 Operational Timing of Power-On Reset Circuit
PSS counter starts
131,072 cycles
LVDON
Reset released
) given by a software timer until the reference voltage
LVDRmin
= 1.0 V and then rises from that
Vss
Vss
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