HD64F36912GFH Renesas Electronics America, HD64F36912GFH Datasheet - Page 296

• Manufacturer Part Number: HD64F36912GFH
• Description: IC H8 MCU FLASH 8K 32-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F36912GFH

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 12MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 15 I
15.4.8
Flowcharts in respective modes that use the I
Rev. 3.00 Sep. 14, 2006 Page 266 of 408
REJ09B0105-0300
No
No
No
Write transmit data in ICDRT
Write transmit data in ICDRT
No
No
No
Read ACKBR in ICIER
Set MST to 1 and TRS
Read BBSY in ICCR2
Read TEND in ICSR
Read TDRE in ICSR
Read TEND in ICSR
Clear TEND in ICSR
Clear STOP in ICSR
Read STOP in ICSR
Clear TDRE in ICSR
Write transmit data
Set MST and TRS
Example of Use
Write 1 to BBSY
Write 0 to BBSY
in ICCR1 to 1.
and 0 to SCP.
to 0 in ICCR1
2
ACKBR=0 ?
BBSY=0 ?
TDRE=1 ?
TEND=1 ?
STOP=1 ?
C Bus Interface 2 (IIC2)
Last byte?
TEND=1 ?
in ICDRT
and SCP
Initialize
Transmit
mode?
Start
End
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Figure 15.17 Sample Flowchart for Master Transmit Mode
No
No
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Mater receive mode
[1] Test the status of the SCL and SDA lines.
[2] Set master transmit mode.
[3] Issue the start candition.
[4] Set the first byte (slave address + R/W) of transmit data.
[5] Wait for 1 byte to be transmitted.
[6] Test the acknowledge transferred from the specified slave device.
[7] Set the second and subsequent bytes (except for the final byte) of transmit data.
[8] Wait for ICDRT empty.
[9] Set the last byte of transmit data.
[10] Wait for last byte to be transmitted.
[11] Clear the TEND flag.
[12] Clear the STOP flag.
[13] Issue the stop condition.
[14] Wait for the creation of stop condition.
[15] Set slave receive mode. Clear TDRE.
2
C bus interface are shown in figures 15.17 to 15.20.