HD64F36912GFH Renesas Electronics America, HD64F36912GFH Datasheet - Page 182
HD64F36912GFH
Manufacturer Part Number
HD64F36912GFH
Description
IC H8 MCU FLASH 8K 32-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36912GFHV.pdf
(442 pages)
Specifications of HD64F36912GFH
Core Processor
H8/300H
Core Size
16-Bit
Speed
12MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
HD64F36912GFH
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 11 Timer V
11.4
11.4.1
1. According to table 11.2, six internal/external clock signals output by prescaler S can be
2. When TCNTV overflows (changes from H'FF to H'00), the overflow flag (OVF) in TCRV0
3. TCNTV is constantly compared with TCORA and TCORB. Compare match flag A or B
4. When a compare match A or B is generated, the TMOV responds with the output value
5. When CCLR1 or CCLR0 in TCRV0 is 01 or 10, TCNTV can be cleared by the corresponding
6. When CCLR1 or CCLR0 in TCRV0 is 11, TCNTV can be cleared by the rising edge of the
7. When a counter-clearing source is generated with TRGE in TCRV1 set to 1, the counting-up is
Rev. 3.00 Sep. 14, 2006 Page 152 of 408
REJ09B0105-0300
Bit
1
0
selected as the timer V operating clock signals. When the operating clock signal is selected,
TCNTV starts counting-up. Figure 11.2 shows the count timing with an internal clock signal
selected, and figure 11.3 shows the count timing with both edges of an external clock signal
selected.
will be set. The timing at this time is shown in figure 11.4. An interrupt request is sent to the
CPU when OVIE in TCRV0 is 1.
(CMFA or CMFB) is set to 1 when TCNTV matches TCORA or TCORB, respectively. The
compare-match signal is generated in the last state in which the values match. Figure 11.5
shows the timing. An interrupt request is generated for the CPU when CMIEA or CMIEB in
TCRV0 is 1.
selected by bits OS3 to OS0 in TCSRV. Figure 11.6 shows the timing when the output is
toggled by compare match A.
compare match. Figure 11.7 shows the timing.
input of TMRIV pin. A TMRIV input pulse-width of at least 1.5 system clocks is necessary.
Figure 11.8 shows the timing.
halted as soon as TCNTV is cleared. TCNTV resumes counting-up when the edge selected by
TVEG1 or TVEG0 in TCRV1 is input from the TGRV pin.
Bit Name
ICKS0
Operation
Timer V Operation
Initial
Value
1
0
R/W
R/W
Description
Reserved
This bit is always read as 1.
Internal Clock Select 0
This bit selects clock signals to input to TCNTV in
combination with CKS2 to CKS0 in TCRV0.
Refer to table 11.2.
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