HD64F36912GFH Renesas Electronics America, HD64F36912GFH Datasheet - Page 266

• Manufacturer Part Number: HD64F36912GFH
• Description: IC H8 MCU FLASH 8K 32-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F36912GFH

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 12MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 14 Serial Communication Interface 3 (SCI3)
14.8
14.8.1
When framing error detection is performed, a break can be detected by reading the RXD pin value
directly. In a break, the input from the RXD pin becomes all 0s, setting the FER flag, and possibly
the PER flag. Note that as SCI3 continues the receive operation after receiving a break, even if the
FER flag is cleared to 0, it will be set to 1 again.
14.8.2
When the TXD bit in PMR1 is 1, the TxD pin is used as an I/O port whose direction (input or
output) and level are determined by PCR and PDR. This can be used to set the TxD pin to mark
state (high level) or send a break during serial data transmission. To maintain the communication
line at mark state until TE is set to 1, set PCR and PDR to 1 respectively, and also set the TXD bit
to 1. At this time, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a
break during serial data transmission, first set PCR to 1 and clear PDR to 0, and then set the TXD
bit to 1. Regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is
output from the TxD pin.
14.8.3
Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
Rev. 3.00 Sep. 14, 2006 Page 236 of 408
REJ09B0105-0300
Usage Notes
Break Detection and Processing
Mark State and Break Sending
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)