MMC2107CFCAG33 Freescale Semiconductor, MMC2107CFCAG33 Datasheet - Page 136

• Manufacturer Part Number: MMC2107CFCAG33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2107
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: Mcore
• Device Core: MCORE
• Device Core Size: 32b
• Frequency (max): 33MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 72
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Supply Voltage (min): 2.7/4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset Controller Module
5.7 Functional Description
5.7.1 Reset Sources
Technical Data
136
This subsection provides a functional description of the MMC2107 reset
controller module.
Table 5-3
controller.
To protect data integrity, a synchronous reset source is not acted upon
by the reset control logic until the end of the current bus cycle. Reset is
then asserted on the next rising edge of the system clock after the cycle
is terminated. Whenever the reset control logic must synchronize reset
to the end of the bus cycle, the internal bus monitor is automatically
enabled regardless of the BME bit setting in the chip configuration
register (CCR). Then if the current bus cycle is not terminated normally,
the bus monitor terminates the cycle based on the length of time
programmed in the BMT field of CCR.
Internal single-byte, half-word, or word writes are guaranteed to
complete without data corruption when a synchronous reset occurs.
External writes, including word writes to 16-bit ports, are also
guaranteed to complete.
Asynchronous reset sources usually indicate a catastrophic failure.
Therefore, the reset control logic does not wait for the current bus cycle
to complete. Reset is asserted immediately to the system.
Power on
External RESET pin (not stop mode)
External RESET pin (during stop mode)
Watchdog timer
Loss of clock
Loss of lock
Software
Freescale Semiconductor, Inc.
For More Information On This Product,
defines the sources of reset and the signals driven by the reset
Go to: www.freescale.com
Reset Controller Module
Table 5-3. Reset Source Summary
Source
MMC2107 – Rev. 2.0
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Type
MOTOROLA