MMC2107CFCAG33 Freescale Semiconductor, MMC2107CFCAG33 Datasheet - Page 478
![IC MCU 33MHZ 128K FLASH 144-LQFP](/photos/12/42/124277/mmc2107cfcag33_sml.jpg)
MMC2107CFCAG33
Manufacturer Part Number
MMC2107CFCAG33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet
1.MMC2107CFCAF33.pdf
(618 pages)
Specifications of MMC2107CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2107
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
72
Number Of Timers
2
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Cpu Family
Mcore
Device Core
MCORE
Device Core Size
32b
Frequency (max)
33MHz
Total Internal Ram Size
8KB
# I/os (max)
72
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
3.6/5.5V
Operating Supply Voltage (min)
2.7/4.5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2107CFCAG33
Manufacturer:
FREESCALE
Quantity:
210
Company:
Part Number:
MMC2107CFCAG33
Manufacturer:
freescaie
Quantity:
35
Company:
Part Number:
MMC2107CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Queued Analog-to-Digital Converter (QADC)
Technical Data
478
NOTE:
The guideline for selecting PSH and PSL is to maintain approximately
50 percent duty cycle; for prescaler values less than 16 or PSH ~=PSL.
For prescaler values greater than 16, keep PSL as large as possible.
Figure 18-42
width signal generator. A 5-bit down counter, clocked at the system clock
rate, is used to create both the high phase and the low phase of the
QCLK signal. At the beginning of the high phase, the 5-bit counter is
loaded with the 5-bit PSH value. When the 0 detector finds that the high
phase is finished, the QCLK is reset. A 3-bit comparator looks for a one’s
complement match with the 3-bit PSL value, which is the end of the low
phase of the QCLK.
These equations define QCLK frequency:
Where:
These are equations for calculating the QCLK high and low phases in
example 1:
These are equations for calculating the QCLK high and low phases in
example 2:
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
PSH = 0 to 31, the prescaler QCLK high cycles in QACR0
PSL = 0 to 7, the prescaler QCLK low cycles in QACR0
f
f
sys
QCLK
= system clock frequency
f
high QCLK time = (11 + 1) ÷ 40
= QCLK frequency
Go to: www.freescale.com
QCLK
high QCLK time = (7 + 1) ÷ 32
low QCLK time = (7 + 1) ÷ 40
low QCLK time = (7 + 1) ÷ 32
shows that the prescaler is essentially a variable pulse
= 1 ÷ (high QCLK time + low QCLK time)
high QCLK time = (PSH + 1) ÷ f
low QCLK time = (PSL + 1) ÷ f
f
f
QCLK
QCLK
= 1/(300 + 200) = 2 MHz
= 1/(250 + 250) = 2 MHz
10
10
10
10
6
6
6
6
= 200 ns
= 250 ns
sys
= 250 ns
sys
= 300 ns
MMC2107 – Rev. 2.0
MOTOROLA
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