MMC2107CFCAG33 Freescale Semiconductor, MMC2107CFCAG33 Datasheet - Page 480

• Manufacturer Part Number: MMC2107CFCAG33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2107
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: Mcore
• Device Core: MCORE
• Device Core Size: 32b
• Frequency (max): 33MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 72
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Supply Voltage (min): 2.7/4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Queued Analog-to-Digital Converter (QADC)
18.10.9 Periodic/Interval Timer
Technical Data
480
NOTE:
Example 1 in
remains high for 12 cycles of the system clock. It also shows that when
PSL = 7, the QCLK remains low for eight system clock cycles. In
Example 2, PSH = 7, and the QCLK remains high for eight cycles of the
system clock. It also shows that when PSL = 7, the QCLK remains low
for eight system clock cycles.
The on-chip periodic/interval timer can be used to generate trigger
events at a programmable interval, initiating execution of queue 1 and/or
queue 2. The periodic/interval timer stays reset under these conditions:
Interval timer single-scan mode does not use the periodic/interval timer
until the single-scan enable bit is set.
These conditions will cause a pulsed reset of the periodic/interval timer
during use:
During the low-power stop mode, the periodic/interval timer is held in
reset. Since low-power stop mode causes QACR1 and QACR2 to be
reset to 0, a valid periodic or interval timer mode must be written after
stop mode is exited to release the timer from reset.
When the IPbus internal FREEZE line is asserted and a periodic or
interval timer mode is selected, the timer counter is reset after the
conversion in progress completes. When the periodic or interval timer
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Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Both queue 1 and queue 2 are programmed to any mode which
does not use the periodic/interval timer.
IPbus system reset is asserted.
Stop mode is selected.
Debug mode is selected.
A queue 1 operating mode change to a mode which uses the
periodic/interval timer, even if queue 2 is already using the timer
A queue 2 operating mode change to a mode which uses the
periodic/interval timer, provided queue 1 is not in a mode which
uses the periodic/interval timer
Roll over of the timer
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Figure 18-43
shows that when PSH = 11, the QCLK
MMC2107 – Rev. 2.0
MOTOROLA