MMC2107CFCAG33 Freescale Semiconductor, MMC2107CFCAG33 Datasheet - Page 389

• Manufacturer Part Number: MMC2107CFCAG33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2107
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: Mcore
• Device Core: MCORE
• Device Core Size: 32b
• Frequency (max): 33MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 72
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Supply Voltage (min): 2.7/4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2107 – Rev. 2.0
MOTOROLA
BEGIN TRANSMISSION
Legend:
CHANGE OUTPUT
CHANGE OUTPUT
SS PIN OUTPUT
MSB FIRST (LSBFE = 0):
LSB FIRST (LSBFE = 1):
t
t
t
t
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE INPUT
MASTER ONLY
L
T
I
L
SLAVE SS PIN
= Minimum idling time between transmissions (minimum SS high time)
, t
= Minimum leading time before the first SCK edge
= Minimum trailing time after the last SCK edge
T
MOSI/MISO
, and t
MOSI PIN
MISO PIN
I
are guaranteed for master mode and required for slave mode.
t
L
Figure 17-11. SPI Clock Format 1 (CPHA = 1)
After the 16th and final SCK edge:
Figure 17-11
The SS pin of the master must be either high or configured as a
general-purpose output not affecting the SPI.
MSB
LSB
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
Data that was in the master SPIDR register is in the slave SPIDR.
Data that was in the slave SPIDR register is in the master SPIDR.
The SCK clock stops and the SPIF flag in SPISR is set, indicating
that the transmission is complete. If the SPIE bit in SPCR1 is set,
SPIF generates an interrupt request.
Serial Peripheral Interface Module (SPI)
BIT 6
BIT 1
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shows the timing of a transmission with the CPHA bit set.
BIT 5
BIT 2
BIT 4
BIT 3
BIT 3
BIT 4
BIT 2
BIT 5
END TRANSMISSION
Serial Peripheral Interface Module (SPI)
BIT 1
BIT 6
MSB
LSB
t
T
Functional Description
MINIMUM 1/2 SCK
t
I
FOR t
t
L
Technical Data
T
, t
L
, t
l
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