MMC2107CFCAG33 Freescale Semiconductor, MMC2107CFCAG33 Datasheet - Page 144

• Manufacturer Part Number: MMC2107CFCAG33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2107
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: Mcore
• Device Core: MCORE
• Device Core Size: 32b
• Frequency (max): 33MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 72
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Supply Voltage (min): 2.7/4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

M•CORE M210 Central Processor Unit (CPU)
6.3 Features
Technical Data
144
The streamlined execution engine uses many of the same performance
enhancements and implementation techniques incorporated in desktop
RISC processors. A strictly defined load/store architecture minimizes
control complexity. Use of a fixed, 16-bit instruction encoding
significantly lowers the memory bandwidth needed to sustain a high rate
of instruction execution, and careful selection of the instruction set
allows the code density and overall memory efficiency of the M•CORE
architecture to surpass those of complex instruction set computer
(CISC) architectures.
These factors reduce system energy consumption significantly, and the
fully static M•CORE design uses other techniques to reduce it even
more. The core uses dynamic clock management to automatically
power-down internal functions that are not in use on a clock-by-clock
basis. It also incorporates three power-conservation operating modes,
which are invoked via dedicated instructions.
The main features of the M•CORE are:
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Freescale Semiconductor, Inc.
M•CORE M210 Central Processor Unit (CPU)
For More Information On This Product,
32-bit load/store RISC architecture
Fixed 16-bit instruction length
16 entry, 32-bit general-purpose register file
Efficient 4-stage execution pipeline, hidden from application
software
Single-cycle execution for most instructions, 2-cycle branches and
memory accesses
Support for byte/half-word/word memory access
Fast interrupt support, with 16 entry user-controlled alternate
register file
Vectored and autovectored interrupt support
On-chip emulation support
Full static design for minimal power consumption
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA