MMC2107CFCAG33 Freescale Semiconductor, MMC2107CFCAG33 Datasheet - Page 498

• Manufacturer Part Number: MMC2107CFCAG33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2107
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: Mcore
• Device Core: MCORE
• Device Core Size: 32b
• Frequency (max): 33MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 72
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Supply Voltage (min): 2.7/4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Queued Analog-to-Digital Converter (QADC)
18.11.7.1 Settling Time for the External Circuit
Technical Data
498
NOTE:
In
is the internal parasitic capacitor. C
sample and hold the input voltage. V
to provide charge to C
The following paragraphs provide a simplified description of the
interaction between the QADC and the user’s external circuitry. This
circuitry is assumed to be a simple RC low-pass filter passing a signal
from a source to the QADC input pin. These simplifying assumptions are
made:
The values for R
determine the length of time required to charge C
level (V
open, disconnecting the internal circuitry from the external circuitry.
Assume that the initial voltage across C
across it is determined by the equation, where t is the total charge time:
As t approaches infinity, V
leakage.) With 10-bit resolution, 1/2 of a count is equal to 1/2048
full-scale value. Assuming worst case (V
shows the required time for C
actual source voltage during 10-bit conversions.
on the RC network in
The following times are completely independent of the A/D converter
architecture (assuming the QADC is not affecting the charging).
Figure
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•
•
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Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
The external capacitor is perfect (no leakage, no significant
dielectric absorption characteristics, etc.)
All parasitic capacitance associated with the input pin is included
in the value of the external capacitor.
Inductance is ignored.
The "on" resistance of the internal switches is 0 ohms and the "off"
resistance is infinite.
SRC
18-54, R
). At time t = 0, V
Go to: www.freescale.com
SRC
F
V
, R
CF
, R
Figure
SRC
samp
= V
F
, and C
CF
and C
SRC
during sample phase.
src
will equal V
18-54.
F
(1 –e
changes in
to charge to within 1/2 of a count of the
F
F
in the user's external circuitry
comprise the external filter circuit. C
Samp
–t/(RF + RSRC) CF
I
is an internal voltage source used
F
is 0. As C
SRC
is the capacitor array used to
SRC
Figure 18-54
. (This assumes no internal
= full scale),
F
Table 18-16
F
to the source voltage
charges, the voltage
)
MMC2107 – Rev. 2.0
while S1 is
Table 18-16
MOTOROLA
is based
P