MMC2107CFCAG33 Freescale Semiconductor, MMC2107CFCAG33 Datasheet - Page 265

• Manufacturer Part Number: MMC2107CFCAG33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2107
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: Mcore
• Device Core: MCORE
• Device Core Size: 32b
• Frequency (max): 33MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 72
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Supply Voltage (min): 2.7/4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2107 – Rev. 2.0
MOTOROLA
EPPA[7:0] — EPORT Pin Assignment Select Fields
The read/write EPPAx fields configure EPORT pins for level detection
and rising and/or falling edge detection as
Pins configured as level-sensitive are inverted so that a logic 0 on the
external pin represents a valid interrupt request. Level-sensitive
interrupt inputs are not latched. To guarantee that a level-sensitive
interrupt request is acknowledged, the interrupt source must keep the
signal asserted until acknowledged by software.
Pins configured as edge-triggered are latched and need not remain
asserted for interrupt generation. A pin configured for edge detection
is monitored regardless of its configuration as input or output.
Interrupt requests generated in the EPORT module can be masked
by the interrupt controller module. EPPAR functionality is
independent of the selected pin direction.
Reset clears the EPPAx fields.
Freescale Semiconductor, Inc.
For More Information On This Product,
EPPAx
00
01
10
11
Edge Port Module (EPORT)
Go to: www.freescale.com
Pin INTx level-sensitive
Pin INTx rising edge triggered
Pin INTx falling edge triggered
Pin INTx both falling edge and rising edge triggered
Table 12-2. EPPAx Field Settings
Pin Configuration
Table 12-2
Edge Port Module (EPORT)
Memory Map and Registers
shows.
Technical Data
265