MMC2107CFCAG33 Freescale Semiconductor, MMC2107CFCAG33 Datasheet - Page 466

• Manufacturer Part Number: MMC2107CFCAG33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2107
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: Mcore
• Device Core: MCORE
• Device Core Size: 32b
• Frequency (max): 33MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 72
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Supply Voltage (min): 2.7/4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Queued Analog-to-Digital Converter (QADC)
18.10.3 Scan Modes
Technical Data
466
Another pause and end-of-queue boundary condition occurs when the
pause and an end-of-queue condition occur in the same CCW. Both the
pause and end-of-queue conditions are recognized simultaneously. The
end-of-queue condition has precedence so a conversion is not
performed for the CCW and the pause flag is not set. The QADC sets the
completion flag and the queue status becomes idle. Examples of this
situation are:
The QADC queuing mechanism allows the application to utilize different
requirements for automatically scanning input channels.
In single-scan mode, a single pass through a sequence of conversions
defined by a queue is performed. In continuous-scan mode, multiple
passes through a sequence of conversions defined by a queue are
executed. The possible modes are:
These paragraphs describe single-scan and continuous-scan
operations.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
The pause bit is set in CCW10 and EOQ is programmed into
CCW10.
During queue 1 operation, the pause bit set in CCW32, which is
also BQ2.
Disabled mode and reserved mode
Software-initiated single-scan mode
External trigger single-scan mode
External gated single-scan mode
Interval timer single-scan mode
Software-initiated continuous-scan mode
External trigger continuous-scan mode
External gated continuous-scan mode
Periodic timer continuous-scan mode
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA