MMC2107CFCAG33 Freescale Semiconductor, MMC2107CFCAG33 Datasheet - Page 419

• Manufacturer Part Number: MMC2107CFCAG33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2107
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: Mcore
• Device Core: MCORE
• Device Core Size: 32b
• Frequency (max): 33MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 72
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Supply Voltage (min): 2.7/4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.8.5.2 Control Register 1
MMC2107 – Rev. 2.0
MOTOROLA
Address: 0x00ca_000c and 0x00ca_000d
Reset:
Reset:
Read:
Read:
Write:
Write:
Control register 1 (QACR1) is the mode control register for the operation
of queue 1. The applications software defines the queue operating mode
for the queue and may enable a completion and/or pause interrupt. Most
of the bits are typically written once when the software initializes the
QADC and not changed afterward.
Stop mode resets the register ($0000)
Read: Anytime
Write: Anytime except stop mode
CIE1 — Queue 1 Completion Interrupt Enable Bit
CIE1 enables an interrupt upon completion of queue 1. The interrupt
request is initiated when the conversion is complete for the CCW in
queue 1.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 = Enable interrupt after the conversion of the sample requested
0 = Disable queue 1 completion interrupt
Bit 15
CIE1
Bit 7
0
0
0
Figure 18-9. QADC Control Register 1 (QACR1)
by the last CCW in queue 1
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= Writes have no effect and the access terminates without a transfer error exception.
PIE1
14
0
6
0
0
SSE1
13
0
0
5
0
0
MQ112
12
0
4
0
0
Queued Analog-to-Digital Converter (QADC)
MQ111
11
0
3
0
0
MQ110
10
0
2
0
0
Register Descriptions
MQ19
9
0
1
0
0
Technical Data
MQ18
Bit 8
Bit 0
0
0
0
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