MMC2107CFCAG33 Freescale Semiconductor, MMC2107CFCAG33 Datasheet - Page 500

• Manufacturer Part Number: MMC2107CFCAG33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2107
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: Mcore
• Device Core: MCORE
• Device Core Size: 32b
• Frequency (max): 33MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 72
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Supply Voltage (min): 2.7/4.5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Queued Analog-to-Digital Converter (QADC)
18.12 Interrupts
18.12.1 Interrupt Operation
Technical Data
500
The four interrupt lines are outputs of the module and have no priority or
arbitration within the module.
QADC inputs can be monitored by polling or by using interrupts. When
interrupts are not needed, software can disable the pause and
completion interrupts and monitor the completion flag and the pause flag
for each queue in the status register (QASR). In other words, flag bits
can be polled to determine when new results are available.
Table 18-18
correspond to queue 1 and queue 2 activity.
If interrupts are enabled for an event, the QADC requests interrupt
service when the event occurs. Using interrupts does not require
continuously polling the status flags to see if an event has taken place.
Queue 1
Queue 2
Queue
Source Impedance
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For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Table 18-18. QADC Status Flags and Interrupt Sources
Table 18-17. Error Resulting From Input Leakage (I
100 k
10 k
1 k
Result written to last CCW in queue 1
Result written for a CCW with pause bit set in
Result written to last CCW in queue 2
Result written for a CCW with pause bit set in
queue 1
queue 2
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shows the status flag and interrupt enable bits which
0.2 counts
Queue Activity
2 counts
100 nA
—
Leakage Value (10-Bit Conversions)
0.4 counts
200 nA
4 count
—
0.1 counts
10 counts
1 counts
500 nA
Status
MMC2107 – Rev. 2.0
Flag
CF1
CF2
PF1
PF2
MOTOROLA
0.2 counts
Off
20 counts
Enable Bit
1000 nA
2 counts
Interrupt
CIE1
CIE2
PIE1
PIE2
)