HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 126

• Manufacturer Part Number: HD6417727F160CV
• Description: IC SH MPU ROMLESS 240QFN
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 2 CPU
The instruction code, operation, and number of execution states of the CPU instructions are shown
in the following tables, classified by instruction type, using the format shown below.
Instruction
Indicated by mnemonic.
Explanation of Symbols
OP.Sz SRC, DEST
Rm: Source register
Rn:
imm: Immediate data
disp: Displacement
Notes: 1. The table shows the minimum number of execution states. In practice, the number of
Rev.6.00 Mar. 27, 2009 Page 68 of 1036
REJ09B0254-0600
OP:
Sz:
SRC: Source
DEST: Destination
Destination register
Operation code
Size
2. Scaled (x1, x2, or x4) according to the instruction operand size, etc.
(1) When there is contention between an instruction fetch and a data access
(2) When the destination register of a load instruction (memory → register) is also used
instruction execution states will be increased in cases such as the following:
by the following instruction
Instruction Code
Indicated in MSB ↔
LSB order.
Explanation of Symbols
mmmm: Source register
nnnn: Destination register
iiii:
dddd:
0000: R0
0001: R1
.........
1111: R15
Immediate data
Displacement *
2
Operation
Indicates summary of
operation.
Explanation of Symbols
→, ←:
(xx):
M/Q/T: Flag bits in the SR
&:
|:
^:
~:
<<n: n-bit left shift
>>n: n-bit right shift
Logical AND of each bit
Logical OR of each bit
Exclusive logical OR of
each bit
Logical NOT of each bit
Transfer direction
Memory operand
Privilege
Indicates a
privileged
instruction.
Execution
States
Value
when no
wait states
are
inserted. *
1
T Bit
Value of T
bit after
instruction
is executed.
Explanation
of Symbols
—: No
change