HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 210

• Manufacturer Part Number: HD6417727F160CV
• Description: IC SH MPU ROMLESS 240QFN
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 5 Cache
5.2.2
CCR2 register is used to enable or disable cache locking mechanism during DSP mode (CPU
status register bit 12) only. Executing a prefetch instruction (PREF) during DSP mode will bring
in one line size of data pointed by Rn to cache, according to the setting of CCR2 [9:8] (W3LOAD,
W3LOCK) and [1:0] (W2LOAD, W2LOCK):
When CCR2[9:8]=11, during DSP mode PREF @Rn will bring the data into way 3. When
CCR2[9:8]=00, 01 or 10 during DSP mode, or any setting during non-DSP mode, PREF @Rn will
place the data into the way pointed by LRU.
When CCR2[1:0]=11, during DSP mode PREF @Rn will bring the data into way 2. When
CCR2[1:0]=00, 01 or 10 during DSP mode, or any setting during non-DSP mode, PREF @Rn will
place the data into the way pointed by LRU.
CCR2 must be set before cache is enabled.
When a PREF instruction is issued and there is a cache hit, the operation is treated as NOP.
Figure 5.3 shows the configuration of the CCR2 register.
The CCR2 register is a write-only register. If read, an undefined value will be returned.
Rev.6.00 Mar. 27, 2009 Page 152 of 1036
REJ09B0254-0600
⎯:
CF:
WT:
CE:
CB:
31
Cache Control Register 2 (CCR2)
…
Reserved bits. These bits are always read as 0. The write value should always be 0.
Cache flush bit. Writing 1 flushes all cache entries (clears the V, U, and LRU bits of all
cache entries to 0). Always reads 0. Write-back to external memory is not performed when
the cache is flushed.
Write-through bit. Indicates the cache's operating mode for areas P0, U0 and P3.
1 = write-through mode, 0 = write-back mode.
Cache enable bit. Indicates whether the cache function is used.
1 = cache used, 0 = cache not used.
Cache write-back bit. Indicates the cache's operating mode for area P1.
1 = write-back mode, 0 = write-through mode.
…
…
Figure 5.2 CCR Register Configuration
…
…
…
…
…
6
5
4
CF
3
CB
2
WT
1
CE
0