HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 145

• Manufacturer Part Number: HD6417727F160CV
• Description: IC SH MPU ROMLESS 240QFN
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 2.31 Correspondence between DSP Instruction Operands and Registers
When writing parallel instructions, the B-field instruction is written first, followed by the A-field
instruction. A sample parallel processing program is shown in figure 2.16.
Square brackets mean that the contents can be omitted.
The no operation instructions NOPX and NOPY can be omitted. Table 2.32 gives an overview of
the B field in parallel operation instructions.
A semicolon is the instruction line delimiter, but this can also be omitted. If the semicolon
delimiter is used, the area to the right of the semicolon can be used as a comment field. This has
the same function as with conventional SH tools.
The DSR register condition code bit (DC) is always updated on the basis of the result of an
unconditional ALU or shift operation instruction. Conditional instructions do not update the DC
bit. Multiply instructions, also, do not update the DC bit. DC bit updating is performed by means
of bits CS0 to CS2 in the DSR register. The DC bit update rules are shown in table 2.33.
Register
DCF
M0
M1
A0
A1
X0
X1
Y0
Y1
PADD A0, M0, A0
PINC X1, A1
PCMP X1, M0
Yes
Yes
Yes
Yes
Sx
Figure 2.16 Sample Parallel Instruction Program
ALU/BPU Operations
PMULS X0, Y0, M0
Yes
Yes
Yes
Yes
Sy
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Dz
MOVX.W @R4+, X0
MOVX.W A0, @R5+R8
MOVX.W @R4
Yes
Yes
Yes
Yes
Du
Rev.6.00 Mar. 27, 2009 Page 87 of 1036
Yes
Yes
Yes
Yes
Se
Multiply Operations
MOVY.W @R6+, Y0 [;]
MOVY.W @R7+, Y0 [;]
[NOPY] [;]
Yes
Yes
Yes
Yes
Sf
REJ09B0254-0600
Section 2 CPU
Yes
Yes
Yes
Yes
Dg