HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 619

• Manufacturer Part Number: HD6417727F160CV
• Description: IC SH MPU ROMLESS 240QFN
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Switching Modes: When switching from receive mode to transmit mode, check that the receive
operation is completed before starting initialization and setting RE to 0 and TE to 1. The RDRF,
PER, and ORER flags can be used to check if reception is completed. When switching from
transmit mode to receive mode, check that the transmit operation is completed before starting
initialization and setting TE to 0 and RE to 1. The TEND flag can be used to check if transmission
is completed.
Interrupt Operation: In the smart card interface mode, there are three types of interrupts:
transmit-data-empty (TXI), communication error (ERI) and receive-data-full (RXI). In this mode,
the transmit-end interrupt (TEI) cannot be requested.
Set the TEND flag in SCSSR to 1 to request a TXI interrupt. Set the RDRF flag in SCSSR to 1 to
request an RXI interrupt. Set the ORER, PER, or FER/ERS flag in SCSSR to 1 to request an ERI
interrupt (table 18.9).
Table 18.9 Smart Card Mode Operating State and Interrupt Sources
Mode
Transmit mode
Receive mode
18.4
When the SCI is used as a smart card interface, be sure that all criteria in sections 18.4.1, Receive
Data Timing and Receive Margin in Asynchronous Mode and 18.4.2, Retransmission (Receive
and Transmit Modes) are applied.
18.4.1
In asynchronous mode, the SCI runs on a basic clock with a frequency of 372 times the transfer
rate. During reception, the SCI0 samples the falling of the start bit using the base clock to achieve
internal synchronization. Receive data is latched internally on the rising edge of the 186th basic
clock cycle (figure 18.8).
Usage Notes
Receive Data Timing and Receive Margin in Asynchronous Mode
State
Normal
Error
Normal
Error
Flag
TEND
FER/ERS
RDRF
PER,
ORER
Rev.6.00 Mar. 27, 2009 Page 561 of 1036
Mask Bit
TIE
RIE
RIE
RIE
Section 18 Smart Card Interface
Interrupt Source
TXI
ERI
RXI
ERI
REJ09B0254-0600