HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 13

• Manufacturer Part Number: HD6417727F160CV
• Description: IC SH MPU ROMLESS 240QFN
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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20.3.7 Procedures for Transmit or Receive
(1) Transmitting in Master
Figure 20.9 Example of Transmit Operation
in Master
(2) Receiving in Master
Figure 20.10 Example of Receive
Operation in Master
(3) Transmitting in Slave
Figure 20.11 Example of Transmit
Operation in Slave
(4) Receiving in Slave
Figure 20.12 Example of Receive
Operation in Slave
(5) A Case of 16 bits Stereo (No.2)
Figure 20.17 Transmit or Receive Timing
(16 bits stereo 2)
Setting: TRMD = 01, REDG = 1,
22.1.1 Block Diagram
Figure 22.1 Block Diagram of USB PIN
Multiplexer
USB2P, USB2M, USB1P, USB1M
No.
1
Settting of SIMDR register,
SIMCR register, SITDAR register,
SIRDAR register, SICDAR register,
SIFCTR register
TDLE = 1,
RDLE = 1,
CD0E = 0,
No.
No.
No.
1
1
1
Settting of SIMDR register,
SIMCR register, SITDAR register,
SIRDAR register, SICDAR register,
SIFCTR register
Settting of SIMDR register,
SIMCR register, SITDAR register,
SIRDAR register, SICDAR register,
SIFCTR register
Settting of SIMDR register,
SIMCR register, SITDAR register,
SIRDAR register, SICDAR register,
SIFCTR register
TDLA3 to TDLA0 = 0000,
RDLA3 to RDLA0 = 0001,
CD0A3 to CD0A0 = 0000,
Time chart
Previous Version
Start
Time chart
Time chart
Time chart
Start
Start
Start
FL = 1101 (frame length 64 bits),
TDRE = 1,
RDRE = 1,
CD1E = 0,
Setting of operation mode,
serial clock, slot position of
transmit or receive data,
slot position of control data
and limit of FIFO request
Setting of operation mode,
serial clock, slot position of
transmit or receive data,
slot position of control data
and limit of FIFO request
Setting of operation mode,
serial clock, slot position of
transmit or receive data,
slot position of control data
and limit of FIFO request
Setting content of SIOF
Setting content of SIOF
Setting content of SIOF
Setting of operation mode,
serial clock, slot position of
transmit or receive data,
slot position of control data
and limit of FIFO request
Setting content of SIOF
TDRA3 to TDRA0 = 0010,
RDRA3 to RDRA0 = 0011,
CD1A3 to CD1A0 = 0000
Setting: TRMD = 11, REDG = 1,
USB2_P, USB2_M, USB1_P, USB1_M
No.
1
Settting of SIMDR register,
SISCR register, SITDAR register,
SIRDAR register, SICDAR register,
SIFCTR register
TDLE = 1,
RDLE = 1,
CD0E = 0,
No.
No.
No.
1
1
1
Rev.6.00 Mar. 27, 2009 Page xi of lvi
Settting of SIMDR register,
SISCR register, SITDAR register,
SIRDAR register, SICDAR register,
SIFCTR register
Settting of SIMDR register,
SISCR register, SITDAR register,
SIRDAR register, SICDAR register,
SIFCTR register
Settting of SIMDR register,
SISCR register, SITDAR register,
SIRDAR register, SICDAR register,
SIFCTR register
TDLA3 to TDLA0 = 0000,
RDLA3 to RDLA0 = 0001,
CD0A3 to CD0A0 = 0000,
Time chart
Revised Version
Start
Time chart
Time chart
Time chart
Start
Start
Start
FL = 1101 (frame length 64 bits),
TDRE = 1,
RDRE = 1,
CD1E = 0,
REJ09B0254-0600
Setting of operation mode,
serial clock, slot position of
transmit or receive data,
slot position of control data
and limit of FIFO request
Setting of operation mode,
serial clock, slot position of
transmit or receive data,
slot position of control data
and limit of FIFO request
Setting of operation mode,
serial clock, slot position of
transmit or receive data,
slot position of control data
and limit of FIFO request
Setting content of SIOF
Setting content of SIOF
Setting content of SIOF
Setting of operation mode,
serial clock, slot position of
transmit or receive data,
slot position of control data
and limit of FIFO request
Setting content of SIOF
TDRA3 to TDRA0 = 0010,
RDRA3 to RDRA0 = 0011,
CD1A3 to CD1A0 = 0000