HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 770

IC SH MPU ROMLESS 240QFN

HD6417727F160CV

Manufacturer Part Number
HD6417727F160CV
Description
IC SH MPU ROMLESS 240QFN
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F160CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
160MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Section 23 USB Function Controller
(5) Status Stage (Control-Out)
The status stage in control-out starts with in-token from the host. In in-token reception at the start
of status stage, an EP0o transfer-request interrupt occurs since no data is in EP0i FIFO. The
application acknowledges that the status stage has started by the interrupt. To transfer 0-byte data
to the host, no data is written to the EP0i FIFO, and 1 is written to the EP0i packet-enable bit.
Therefore, 0-byte data is transferred to the host in the next in-token, and control transfer is
completed.
However, after the application completes all processing related to the data stage, write 1 to the
EP0i packet-enable bit.
Rev.6.00 Mar. 27, 2009 Page 712 of 1036
REJ09B0254-0600
0-byte transmission to host
Set EP0i transfer-end flag
(USBIFR0/EP0i TS = 1)
End of control transfer
IN token reception
in EP0i FIFO?
Valid data
USB function
Figure 23.9 Status Stage Operation (Control-Out)
Yes
ACK
NACK
No
Interrupt request
Interrupt request
Clear EP0i transfer-end flag
Clear EP0i transfer-request
(USBTRG/EP0i PKTE = 1)
(USBIFR0/EP0i TR = 0)
(USBIFR0/EP0i TS = 0)
Write 1 to EP0i packet
End of control transfer
Application
enable bit
flag

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