HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 32

• Manufacturer Part Number: HD6417727F160CV
• Description: IC SH MPU ROMLESS 240QFN
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

23.6 Operation........................................................................................................................... 704
23.7 Processing of USB Standard Commands and Class/Vendor Commands.......................... 717
23.8 Stall Operations................................................................................................................. 718
23.9 Usage Notes ...................................................................................................................... 722
Section 24 USB HOST Module
24.1 General Description .......................................................................................................... 725
24.2 Register Description.......................................................................................................... 728
Rev.6.00 Mar. 27, 2009 Page xxx of lvi
REJ09B0254-0600
23.5.8 USB Interrupt Flag Register 1 (USBIFR1).......................................................... 697
23.5.9 USB Trigger Register (USBTRG) ....................................................................... 698
23.5.10 USBFIFO Clear Register (USBFCLR)................................................................ 699
23.5.11 USBEP0o Receive Data Size Register (USBEPSZ0O) ....................................... 699
23.5.12 USB Data Status Register (USBDASTS) ............................................................ 700
23.5.13 USB Endpoint Stall Register (USBEPSTL) ........................................................ 700
23.5.14 USB Interrupt Enable Register 0 (USBIER0)...................................................... 701
23.5.15 USB Interrupt Enable Register 1 (USBIER1)...................................................... 701
23.5.16 USBEP1 Receive Data Size Register (USBEPSZ1) ............................................ 701
23.5.17 USB Interrupt Select Register 0 (USBISR0) ....................................................... 702
23.5.18 USB Interrupt Select Register 1 (USBISR1) ....................................................... 702
23.5.19 USBDMA Setting Register (USBDMAR)........................................................... 703
23.6.1 Cable Connection................................................................................................. 704
23.6.2 Cable Disconnection ............................................................................................ 705
23.6.3 Control Transfer................................................................................................... 706
23.6.4 EP1 Bulk-Out Transfer (Dual FIFOs).................................................................. 713
23.6.5 EP2 Bulk-In Transfer (Dual FIFOs) .................................................................... 714
23.6.6 EP3 Interrupt-In Transfer..................................................................................... 716
23.7.1 Processing of Commands Transmitted by Control Transfer ................................ 717
23.8.1 Overview.............................................................................................................. 718
23.8.2 Forcible Stall by Application ............................................................................... 718
23.8.3 Automatic Stall by USB Function Module .......................................................... 720
23.9.1 Receiving Setup Data........................................................................................... 722
23.9.2 Clearing the FIFO ................................................................................................ 722
23.9.3 Overreading and Overwriting the Data Registers ................................................ 722
23.9.4 Assigning Interrupt Sources to EP0 ..................................................................... 723
23.9.5 Clearing the FIFO when DMA Transfer Is Enabled ............................................ 723
23.9.6 Notes on TR Interrupt .......................................................................................... 723
23.9.7 Peripheral Clock (Pφ) Operation Frequency ........................................................ 724
24.1.1 Features................................................................................................................ 725
24.1.2 Pin Configuration................................................................................................. 726
24.1.3 Register Configuration......................................................................................... 727
24.2.1 HcRevision........................................................................................................... 728
...................................................................................... 725