HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 326

IC SH MPU ROMLESS 240QFN

HD6417727F160CV

Manufacturer Part Number
HD6417727F160CV
Description
IC SH MPU ROMLESS 240QFN
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F160CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
160MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Section 10 On-Chip Oscillation Circuits
Bits 14, 3 and 2—Internal Clock Frequency Division Ratio (IFC2, IFC1, IFC0): These bits
specify the frequency division ratio of the internal clock with respect to the output frequency of
PLL circuit 1.
Bit 14: IFC2
0
0
1
0
Values other than above
Note: Do not set the internal clock frequency lower than the CKIO frequency.
Bits 13, 1 and 0—Peripheral Clock Frequency Division Ratio (PFC2, PFC1, PFC0): These
bits specify the division ratio of the peripheral clock frequency with respect to the frequency of the
output frequency of PLL circuit 1 or the frequency of the CKIO pin.
Bit 13: PFC2
0
0
1
0
1
Values other than above
Note: Do not set the peripheral clock frequency higher than the frequency of the CKIO pin.
Bits 12 to 9, 7 and 6—Reserved: These bits are always read as 0. The write value should always
be 0.
Bit 8—Reserved: This bit is always read as 1. The write value should always be 1.
Rev.6.00 Mar. 27, 2009 Page 268 of 1036
REJ09B0254-0600
Bit 3: IFC1
0
0
0
1
Bit 1: PFC1
0
0
0
1
0
Bit 2: IFC0
0
1
0
0
Bit 0: PFC0
0
1
0
0
1
Description
× 1
× 1/2
× 1/3
× 1/4
Reserved (illegal setting)
Description
× 1
× 1/2
× 1/3
× 1/4
× 1/6
Reserved (illegal setting)
(Initial value)
(Initial value)

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