HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 274

• Manufacturer Part Number: HD6417727F160CV
• Description: IC SH MPU ROMLESS 240QFN
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 User Break Controller
Bit 20—Break ASID Mask B (BASMB): Specifies whether the bits of channel B break ASID7
to ASID0 (BASB7 to BASB0) set in BASRB are masked or not.
Bit 20: BASMB Description
0
1
Bits 19 to 16—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 15—CPU Condition Match Flag A (SCMFCA): When the CPU bus cycle condition in the
break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to
clear this flag, write 0 into this bit.
Bit 15:
SCMFCA
0
1
Bit 14—CPU Condition Match Flag B (SCMFCB): When the CPU bus cycle condition in the
break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to
clear this flag, write 0 into this bit.
Bit 14:
SCMFCB
0
1
Bit 13—DMAC Condition Match Flag A (SCMFDA): When the on-chip DMAC bus cycle
condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to
0). In order to clear this flag, write 0 into this bit.
Bit 13:
SCMFDA
0
1
Rev.6.00 Mar. 27, 2009 Page 216 of 1036
REJ09B0254-0600
All BASRB bits are included in break condition, and ASID is checked
(Initial value)
No BASRB bits are included in break condition, and ASID is not checked
Description
The CPU cycle condition for channel A does not match
The CPU cycle condition for channel A matches
Description
The CPU cycle condition for channel B does not match
The CPU cycle condition for channel B matches
Description
The DMAC cycle condition for channel A does not match
The DMAC cycle condition for channel A matches
(Initial value)
(Initial value)
(Initial value)