HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 40

• Manufacturer Part Number: HD6417727F160CV
• Description: IC SH MPU ROMLESS 240QFN
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 3.14 MMU Exception in Repeat Loop ........................................................................... 123
Figure 3.15 Specifying Address and Data for Memory-Mapped TLB Access .......................... 126
Section 4 Exception Handling
Figure 4.1
Figure 4.2
Figure 4.3
Section 5 Cache
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Figure 5.5
Figure 5.6
Section 6 X/Y Memory
Figure 6.1
Figure 6.2
Section 7 Interrupt Controller (INTC)
Figure 7.1
Figure 7.2
Figure 7.3
Figure 7.4
Section 8 User Break Controller
Figure 8.1
Section 9 Power-Down Modes and Software Reset
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 9.5
Figure 9.6
Figure 9.7
Figure 9.8
Figure 9.9
Figure 9.10 Hardware Standby Mode Timing (CA = Low in Normal Operation) .................... 255
Rev.6.00 Mar. 27, 2009 Page xxxviii of lvi
REJ09B0254-0600
Vector Table........................................................................................................... 132
Example of Acceptance Order of General Exceptions ........................................... 135
Bit Configurations of EXPEVT, INTEVT, INTEVT2, and TRA Registers .......... 139
Cache Structure ...................................................................................................... 150
CCR Register Configuration .................................................................................. 152
CCR2 Register Configuration ................................................................................ 153
Cache Search Scheme ............................................................................................ 155
Write-Back Buffer Configuration........................................................................... 157
Specifying Address and Data for Memory-Mapped Cache Access........................ 159
X/Y Memory Logical Address Mapping................................................................ 163
X/Y Memory Physical Address Mapping .............................................................. 164
INTC Block Diagram ............................................................................................. 166
Example of IRL Interrupt Connection.................................................................... 171
Interrupt Operation Flowchart................................................................................ 198
Example of Pipeline Operations when IRL Interrupt is Accepted ......................... 202
Block Diagram of User Break Controller............................................................... 204
Canceling Standby Mode with STBCR.STBY....................................................... 246
Power-On Reset (Clock Modes 0, 1, 2, and 7) STATUS Output ........................... 249
Manual Reset STATUS Output.............................................................................. 250
Standby to Interrupt STATUS Output.................................................................... 250
Standby to Power-On Reset STATUS Output ....................................................... 251
Standby to Manual Reset STATUS Output............................................................ 251
Sleep to Interrupt STATUS Output........................................................................ 252
Sleep to Power-On Reset STATUS Output............................................................ 252
Sleep to Manual Reset STATUS Output................................................................ 253