HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 403

• Manufacturer Part Number: HD6417727F160CV
• Description: IC SH MPU ROMLESS 240QFN
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed
after powering on. To perform synchronous DRAM initialization correctly, the bus state controller
registers must first be set, followed by a write to the synchronous DRAM mode register. In
synchronous DRAM mode register setting, the address signal value at that time is latched by a
combination of the RAS, CAS, and RD/WR signals. If the value to be set is X, the bus state
controller provides for value X to be written to the synchronous DRAM mode register by
performing a write to address H'FFFFD000 + X for area 2 synchronous DRAM, and to address
H'FFFFE000 + X for area 3 synchronous DRAM. In this operation the data is ignored, but the
mode write is performed as a byte-size access. To set burst read/single write, CAS latency 1 to 3,
wrap type = sequential, and burst length 1 supported by this LSI, arbitrary data is written in a byte-
size access to the following addresses.
Mode register setting timing is shown in figure 12.21.
As a result of the write to address H'FFFFD000 + X or H'FFFFE000 + X, a precharge all banks
(PALL) command is first issued in the TRp1 cycle, then a mode register write command is issued
in the TMw1 cycle.
Address signals, when the mode-register write command is issued, are as follows:
Before mode register setting, a 100 µs idle time (depending on the memory manufacturer) must be
guaranteed after powering on requested by the synchronous DRAM. If the reset signal pulse width
is greater than this idle time, there is no problem in performing mode register setting immediately.
The number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must
be executed. This is usually achieved automatically while various kinds of initialization are being
With 32-bit bus width:
CAS latency 1
CAS latency 2
CAS latency 3
With 16-bit bus width:
CAS latency 1
CAS latency 2
CAS latency 3
A15 to A9 = 0000100 (burst read and single write)
A8 to A6 = CAS latency
A5 = 0 (burst type = sequential)
A4 to A2 = 000 (burst length 1)
Area 2
FFFFD840
FFFFD880
FFFFD8C0
Area 2
FFFFD420
FFFFD440
FFFFD460
Area 3
Area 3
FFFFE840
FFFFE880
FFFFE8C0
FFFFE420
FFFFE440
FFFFE460
Rev.6.00 Mar. 27, 2009 Page 345 of 1036
Section 12 Bus State Controller (BSC)
REJ09B0254-0600