HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 341

• Manufacturer Part Number: HD6417727F160CV
• Description: IC SH MPU ROMLESS 240QFN
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

12.1
The bus state controller (BSC) divides physical address space and output control signals for
various types of memory and bus interface specifications. BSC functions enable this LSI to link
directly with synchronous DRAM, SRAM, ROM, and other memory storage devices without an
external circuit. The BSC also allows direct connection to PCMCIA interfaces, simplifying system
design and allowing high-speed data transfers in a compact system.
12.1.1
The BSC has the following features:
• Physical address space is divided into six areas
• Direct interface to synchronous DRAM (except if clock ratio Iφ:Bφ = 1:1)
• Burst ROM interface
• PCMCIA direct-connection interface*
⎯ A maximum 64 Mbytes for each of the six areas, 0, 2 to 6
⎯ Area bus width can be selected by register (area 0 is set by external pin)
⎯ Wait states can be inserted using the WAIT pin
⎯ Wait state insertion can be controlled through software. Register settings can be used to
⎯ The type of memory connected can be specified for each area, and
⎯ Control signals are output for direct memory connection
⎯ Wait cycles are automatically inserted to avoid data bus conflict for continuous memory
⎯ Multiplexes row/column addresses according to synchronous DRAM capacity
⎯ Supports burst operation
⎯ Has both auto-refresh and self-refresh functions
⎯ Controls timing of synchronous DRAM direct-connection control signals according to
⎯ Insertion of wait states controllable through software
⎯ Register setting control of burst transfers
⎯ Insertion of wait states controllable through software
⎯ Bus sizing function for I/O bus width (only in the little endian mode)
specify the insertion of 1–10 cycles independently for each area (1–38 cycles for areas 5
and 6 and the PCMCIA interface only)
accesses to different areas or writes directly following reads of the same area
register setting
Overview
Features
Section 12 Bus State Controller (BSC)
Rev.6.00 Mar. 27, 2009 Page 283 of 1036
Section 12 Bus State Controller (BSC)
REJ09B0254-0600