HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 660

• Manufacturer Part Number: HD6417727F160CV
• Description: IC SH MPU ROMLESS 240QFN
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 Serial Communication Interface with FIFO (SCIF)
5. TEND Flag and TE Bit Processing: The TEND flag is set to 1 during transmission of the stop
6. Receive Data Sampling Timing and Receive Margin: The SCIF operates on a base clock with a
Rev.6.00 Mar. 27, 2009 Page 602 of 1036
REJ09B0254-0600
bit of the last data. Consequently, if the TE bit is cleared to 0 immediately after setting of the
TEND flag has been confirmed, the stop bit will be in the process of transmission and will not
be transmitted normally. Therefore, the TE bit should not be cleared to 0 for at least 0.5 serial
clock cycles (or 1.5 cycles if two stop bits are used) after setting of the TEND flag setting is
confirmed.
frequency of 16 times the transfer rate. In reception, the SCIF synchronizes internally with the
fall of the start bit, which it samples on the base clock. Receive data is latched at the rising
edge of the eighth base clock pulse. The timing is shown in figure 19.12.
The receive margin in asynchronous mode can therefore be expressed as shown in equation
(1).
Equation 1:
data (RxD2)
Base clock
Synchro-
sampling
sampling
M = 0.5 −
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
Receive
nization
timing
timing
Data
Figure 19.12 Receive Data Sampling Timing in Asynchronous Mode
0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5
2N
1
8 clocks
Start bit
− (L − 0.5) F −
16 clocks
−7.5 clocks
D − 0.5
N
(1 + F) × 100%
+7.5 clocks
D0
........................ (1)
D1