HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 271

• Manufacturer Part Number: HD6417727F160CV
• Description: IC SH MPU ROMLESS 240QFN
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.2.8
Break bus cycle register B (BBRB) is a 16-bit read/write register, which specifies (1) logic or
internal bus (L or I bus), X bus, of Y bus, (2) CPU cycle or DMAC cycle, (3) instruction fetch or
data access, (4) read/write, and (5) operand size in the break conditions of channel B. A power-on
reset initializes BBRB to H'0000.
Bits 15 to 10—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 9—X/Y Memory Bus Enable (XYE): Selects the logic bus or internal bus (L bus or I bus) or
the X/Y memory bus as the bus of the channel B break condition.
Bit 9: XYE
0
1
Bits 8—X or Y Memory Bus Select (XYS): Selects the X bus or the Y bus as the bus of the
channel B break condition.
Bit 8: XYS
0
1
Bits 7 and 6—CPU Cycle/DMAC Cycle Select B (CDB1 and CDB0): Select the CPU cycle or
DMAC cycle as the bus cycle of the channel B break condition.
Bit 7: CDB1
0
*
1
Note: * Don’t care.
Initial value:
R/W:
Bit:
Break Bus Cycle Register B (BBRB)
15
—
R
0
Description
Select internal bus (I bus) for the channel B break condition
Select X/Y memory bus (X/Y bus) for the channel B break condition
Description
Select the X bus for the channel B break condition
Select the Y bus for the channel B break condition
Bit 6: CDB0
0
1
0
14
—
R
0
13
—
R
0
12
—
R
0
11
Description
Condition comparison is not performed
The break condition is the CPU cycle
The break condition is the DMAC cycle
—
R
0
10
—
R
0
XYE
R/W
9
0
XYS CDB1 CDB0 IDB1 IDB0 RWB1 RWB0 SZB1 SZB0
R/W
8
0
Rev.6.00 Mar. 27, 2009 Page 213 of 1036
R/W
7
0
R/W
6
0
Section 8 User Break Controller
R/W
5
0
R/W
4
0
R/W
3
0
REJ09B0254-0600
R/W
2
0
(Initial value)
R/W
1
0
R/W
0
0