HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 595

• Manufacturer Part Number: HD6417727F160CV
• Description: IC SH MPU ROMLESS 240QFN
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 17.23 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
Note: When switching transmit or receive operation to simultaneous serial transmit and receive
No
No
No
operations, first clear the TE bit and RE bit to 0, and then set both these bits to 1
simultaneously.
and clear RDRF bit in SCSSR to 0
Write transmission data to SCTDR
and clear TDRE bit in SCSSR to 0
Read receive data of SCRDR
Start transmission/reception
End transmission/reception
Read ORER bit in SCSSR
Read TDRE bit in SCSSR
Read RDRF bit in SCSSR
transmitted/received?
Clear TE and RE bits
in SCSCR to 0
ORER = 1?
TDRE = 1?
RDRF = 1?
All data
Yes
No
Yes
Yes
Error processing
Yes
(1)
(3)
(4)
Section 17 Serial Communication Interface (SCI)
(2)
Rev.6.00 Mar. 27, 2009 Page 537 of 1036
(1) SCI status check and transmit
(2) Receive error processing:
(3) SCI status check and receive data
(4) To continue transmitting and
data write:
Read the serial status register
(SCSSR), check that the TDRE bit
is 1, then write transmit data in the
transmit data register (SCTDR)
and clear TDRE to 0. The TXI
interrupt can also be used to
determine if the TDRE bit has
changed from 0 to 1.
If a receive error occurs, read the
ORER bit in SCSSR to identify the
error. After executing the
necessary error processing, clear
ORER to 0. Transmitting/receiving
cannot resume if ORER remains
set to 1.
read:
Read the serial status register
(SCSSR), check that RDRF is set
to 1, then read receive data from
the receive data register (SCRDR)
and clear RDRF to 0. The RXI
interrupt can also be used to
determine if the RDRF bit has
changed from 0 to 1.
receiving serial data:
Read the RDRF bit and SCRDR,
and clear RDRF to 0 before the
frame MSB (bit 7) of the current
frame is received. Also read the
TDRE bit to check whether it is
safe to write (if it reads 1); if so,
write data in SCTDR, then clear
TDRE to 0 before the MSB (bit 7)
of the current frame is transmitted.
REJ09B0254-0600