HD6417727F160CV Renesas Electronics America, HD6417727F160CV Datasheet - Page 487

• Manufacturer Part Number: HD6417727F160CV
• Description: IC SH MPU ROMLESS 240QFN
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

14.3.7
DMA transfer ending conditions to terminate transfer differ according to the ending types,
individual channel ending and all channel ending. At a transfer end, the following conditions are
applied except the case when the DMA transfer count register (DMATCR) value reaches 0.
(a) Cycle-steal mode (external request, internal request, and auto request)
(b) Burst mode, edge detection (external request, internal request, and auto request)
(c) Burst mode, level detection (external request)
(d) Bus timing when transfers are suspended
When a transfer ending condition is satisfied, DMAC transfer request acceptance is suspended.
The DMAC stops operation after completing the number of transfers that has accepted before
the ending conditions are satisfied.
In the cycle-steal mode, the same operation is provided regardless of the transfer request
detection method; the level detection or the edge detection.
The timing of DMAC operation ending after an ending condition is satisfied differs from that
in cycle steal mode. In the edge detection in the burst mode, though only one transfer request
is generated at the DMAC start-up, a stop request sampling is performed in the same timing as
a transfer request sampling in the cycle-steal mode. As a result, the period when a stop request
is not sampled is regarded as the period when a transfer request is generated, and after
performing the DMA transfer for this period, the DMAC stops operation.
Same as described in (a).
Transfer is suspended when one transfer ends. Even if a transfer ending condition is satisfied
during a read with the direct address transfer in the dual address mode, the subsequent write
process is executed, and after the transfer in (a) to (c) above has been executed, DMAC
operation suspends.
DMA Transfer Ending
Section 14 Direct Memory Access Controller (DMAC)
Rev.6.00 Mar. 27, 2009 Page 429 of 1036
REJ09B0254-0600