UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 12

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 17 I
16.4
16.5
16.6
16.7
16.8
16.9
17.1
17.2
17.3
17.4
17.5
17.6
17.7
17.8
17.9
17.10 Error Detection...................................................................................................................... 567
17.11 Extension Code..................................................................................................................... 567
17.12 Arbitration ............................................................................................................................. 568
17.13 Wakeup Function.................................................................................................................. 569
Registers ............................................................................................................................... 468
Interrupt Request Signals.................................................................................................... 475
Operation............................................................................................................................... 476
16.6.1
16.6.2
16.6.3
16.6.4
16.6.5
16.6.6
16.6.7
16.6.8
16.6.9
16.6.10 Continuous transfer mode (slave mode, transmission mode) ..................................................497
16.6.11 Continuous transfer mode (slave mode, reception mode) .......................................................499
16.6.12 Continuous transfer mode (slave mode, transmission/reception mode) ..................................502
16.6.13 Reception error ........................................................................................................................506
16.6.14 Clock timing .............................................................................................................................507
Output Pins ........................................................................................................................... 509
Baud Rate Generator............................................................................................................ 510
16.8.1
Cautions ................................................................................................................................ 512
Mode Switching of I
17.1.1
17.1.2
Features................................................................................................................................. 515
Configuration ........................................................................................................................ 516
Registers ............................................................................................................................... 520
I
17.5.1
I
17.6.1
17.6.2
17.6.3
17.6.4
17.6.5
17.6.6
17.6.7
I
17.7.1
17.7.2
17.7.3
17.7.4
17.7.5
17.7.6
Interrupt Request Signal (INTIICn) Generation Timing and Wait Control....................... 565
Address Match Detection Method ...................................................................................... 567
2
2
2
C Bus Mode Functions....................................................................................................... 536
C Bus Definitions and Control Methods .......................................................................... 537
C Interrupt Request Signals (INTIICn) .............................................................................. 545
2
C BUS .......................................................................................................................... 513
Single transfer mode (master mode, transmission mode)........................................................476
Single transfer mode (master mode, reception mode) .............................................................478
Single transfer mode (master mode, transmission/reception mode) ........................................480
Single transfer mode (slave mode, transmission mode) ..........................................................482
Single transfer mode (slave mode, reception mode)................................................................484
Single transfer mode (slave mode, transmission/reception mode)...........................................486
Continuous transfer mode (master mode, transmission mode) ...............................................488
Continuous transfer mode (master mode, reception mode).....................................................490
Continuous transfer mode (master mode, transmission/reception mode)................................493
Baud rate generation ...............................................................................................................511
UARTA2 and I
CSIB0 and I
Pin configuration ......................................................................................................................536
Start condition..........................................................................................................................537
Addresses................................................................................................................................538
Transfer direction specification ................................................................................................539
ACK .........................................................................................................................................540
Stop condition ..........................................................................................................................541
Wait state.................................................................................................................................542
Wait state cancellation method ................................................................................................544
Master device operation...........................................................................................................545
Slave device operation (when receiving slave address data (address match))........................548
Slave device operation (when receiving extension code) ........................................................552
Operation without communication............................................................................................556
Arbitration loss operation (operation as slave after arbitration loss).........................................556
Operation when arbitration loss occurs (no communication after arbitration loss) ...................558
2
C01 mode switching ............................................................................................514
2
2
C Bus and Other Serial Interfaces ................................................... 513
C00 mode switching.........................................................................................513