UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 368

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UPD70F3735GC-GAD-AX

Manufacturer Part Number
UPD70F3735GC-GAD-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3735GC-GAD-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
66
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3735GC-GAD-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
V850ES/JF3-L
detected, the count value of the 16-bit counter is stored in the TQ0CCRm register, the 16-bit counter is cleared to 0000H,
and a capture interrupt request signal (INTTQ0CCm) is generated.
request signal (INTTQ0OV) is generated at the next count clock, and the counter is cleared to 0000H and continues
counting. At this time, the overflow flag (TQ0OPT0.TQ0OVF bit) is also set to 1. Clear the overflow flag to 0 by executing
the CLR instruction via software.
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
When the TQ0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIQ0m pin is later
The pulse width is calculated as follows.
If the valid edge is not input to the TIQ0m pin even when the 16-bit counter counted up to FFFFH, an overflow interrupt
If the overflow flag is set to 1, the pulse width can be calculated as follows.
Remark
Pulse width = Captured value × Count clock cycle
Pulse width = (10000H × TQ0OVF bit set (1) count + Captured value) × Count clock cycle
INTTQ0CCm signal
Remark
TQ0CCRm register
INTTQ0OV signal
m = 0 to 3
TIQ0m pin input
16-bit counter
TQ0OVF bit
TQ0CE bit
m = 0 to 3
FFFFH
0000H
Figure 8-35. Basic Timing in Pulse Width Measurement Mode
0000H
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
D
0
D
1
Cleared to 0 by
CLR instruction
D
2
D
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