UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 550

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
(7) IIC division clock select registers 0, 1 (OCKS0, OCKS1)
(8) IIC shift registers 0, 1 (IIC0, IIC1)
The OCKSm register controls the I
These registers control the I
register.
These registers can be read or written in 8-bit units.
Reset sets these registers to 00H.
The IICn register is used for serial transmission/reception (shift operations) synchronized with the serial clock.
These registers can be read or written in 8-bit units, but data should not be written to the IICn register during a data
transfer.
Access (read/write) the IICn register only during the wait period. Accessing this register in communication states
other than the wait period is prohibited. However, for the master device, the IICn register can be written once only
after the transmission trigger bit (IICCn.STTn bit) has been set to 1.
A wait state is released by writing the IICn register during the wait period, and data transfer is started (n = 0, 1).
Reset sets these registers to 00H.
After reset: 00H
(n = 0, 1)
IICn
OCKSm
(m = 0, 1)
After reset: 00H
OCKSTHm
OCKSENm
7
0
0
0
0
1
0
1
0
R/W
Other than above
R/W
2
Disable I
Enable I
OCKSm1
C00 division clock via the OCKS0 register and the I
6
0
0
0
1
1
0
2
C0n division clock (n = 0, 1).
Address: OCKS0 FFFFF340H, OCKS1 FFFFF344H
2
2
C division clock operation
C division clock operation
OCKSm0
Address: IIC0 FFFFFD80H, IIC1 FFFFFD90H
0
1
0
1
0
0
5
Operation setting of I
OCKSENm OCKSTHm
f
f
f
f
f
Setting prohibited
XX
XX
XX
XX
XX
/2
/3
/4
/5
4
Selection of I
2
C division clock
3
2
C division clock
0
2
OCKSm1 OCKSm0
2
C01 division clock via the OCKS1
1
CAPTER 17 I
0
Page 534 of 816
2
C BUS