UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 754

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
29.1.3 Maskable functions
29.1.4 Register
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
Reset, NMI, INTWDT2, WAIT, and HLDRQ signals can be masked.
The maskable functions with the debugger (ID850QB) and the corresponding V850ES/JF3-L functions are listed below.
(1) On-chip debug mode register (OCDM)
The OCDM register is used to specify whether a pin provided with an on-chip debug function is used as an on-chip
debug pin or as an ordinary port/peripheral function pin. It also is used to disconnect the internal pull-down resistor
of the P05/INTP2/DRST pin.
This register is a special register and can be written only in a combination of specific sequences (see 3.4.7
Special registers).
The OCDM register can be written only while a low level is input to the DRST pin.
This register can be read or written in 8-bit or 1-bit units.
NMI0
NMI2
STOP
HOLD
RESET
WAIT
Maskable Functions with ID850QB
Table 29-2. Maskable Functions
NMI pin input
Non-maskable interrupt request signal
(INTWDT2) generation
HLDRQ pin input
Reset signal generation by RESET pin input,
low-voltage detector, clock monitor, or
watchdog timer (WDT2) overflow
WAIT pin input
Corresponding V850ES/JF3-L Functions
CHAPTER 29 ON-CHIP DEBUG FUNCTION
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