UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 832

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
D.1 Major Revisions in This Edition
D.2 Revision History of Previous Editions
applied.
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
3rd
2nd
p. 454
p. 454
p. 781
p. 782
Edition
A history of the revisions up to this edition is shown below. “Applied to:” indicates the chapters to which the revision was
Page
Modification of 2.1 (2) Non-port pins
Modification of 12.3 (2) Real-time output port control register 0 (RTPC0)
Modification of Table 15-4. Maximum/Minimum Allowable Baud Rate Error
• Under development → mass production
Modification of status of pins AD15 to AD0 in Table 5-2 Pin Statuses When
Internal ROM, Internal RAM, or On-Chip Peripheral I/O Is Accessed
Modification of status of pins AD15 to AD0 in Table 5-2 Pin Statuses When
Internal ROM, Internal RAM, or On-Chip Peripheral I/O Is Accessed
Modification of 16.2 Features
Modification of Note in 16.4 (2) CSIBn control register 1 (CBnCTL1)
Modification of Caution in 16.8.1 Baud rate generation
Modification of description in 18.13 (4) (a) Temporarily stop transfer of all
DMA channels
Modification of Table 28-2 Basic Functions
Modification of Table 28-3 Security Functions
Modification of Table 28-4 Security Setting
Modification of Table 28-7 Flash Memory Control Commands
Modification of Main Clock Oscillator Characteristics in CHAPTER 30
ELECTRICAL SPECIFICATIONS
Modification of Subclock Oscillator Characteristics in CHAPTER 30
ELECTRICAL SPECIFICATIONS
Modification of DC Characteristics in CHAPTER 30 ELECTRICAL
SPECIFICATIONS
Modification of Bus Timing (b) Read/write cycle (CLKOUT synchronous):
In multiplexed bus mode in CHAPTER 30 ELECTRICAL
SPECIFICATIONS
Modification of Bus Timing UART Timing in CHAPTER 30 ELECTRICAL
SPECIFICATIONS
Modification of Bus Timing CSIB Timing in CHAPTER 30 ELECTRICAL
SPECIFICATIONS
Addition of CHAPTER 32 RECOMMENDED SOLDERING CONDITIONS
Addition of APPENDIX D REVISION HISTORY
μ
GAD-AX,
PD70F3735GK-GAK-AX,
Modification of Caution in 15.6.10 Receive data noise filter
Modification of Figure 15-13 Timing of RXDAn Signal Judged as Noise
Modification of Flash Memory Programming Characteristics
Addition of Remark to (3) Programming characteristics
μ
PD70F3736GC-GAD-AX
μ
PD70F3736GK-GAK-AX,
APPENDIX D REVISION HISTORY
Description
μ
PD70F3735GC-
Description
APPENDIX D REVISION HISTORY
CHAPTER 2 PIN FUNCTIONS
CHAPTER 12 REAL-TIME OUTPUT
FUNCTION (RTO)
CHAPTER
SERIAL INTERFACE A (UARTA)
Throughout
CHAPTER 5 BUS CONTROL
FUNCTION
CHAPTER 16 3-WIRE VARIABLE-
LENGTH SERIAL I/O (CSIB)
CHAPTER 18 DMA FUNCTION (DMA
CONTROLLER)
CHAPTER 28 FLASH MEMORY
CHAPTER 30 ELECTRICAL
SPECIFICATIONS
CHAPTER 32 RECOMMENDED
SOLDERING CONDITIONS
APPENDIX D REVISION HISTORY
15
Applied to:
ASYNCHRONOUS
Page 816 of 816